UPD72862 datasheet(10/36 Pages) NEC

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Data Sheet S14265EJ2V0DS00

µµµµPD72862

1.3 PHY/Link Interface Signals: (15 pins)

Name

I/O

Pin No.

IOL

Volts(V)

Function

D0-D7

I/O

59-62,

64-67

9mA

3.3

PHY/Link Bi-directional Data (ISO-barrier supported)

CTL0,CTL1

I/O

69, 70

9mA

3.3

PHY/Link Bi-directional Control (ISO-barrier supported)

LREQ

9mA

3.3

PHY/Link Request (ISO-barrier supported)

LINKON

3.3

Link-On Request (ISO-barrier supported)

LPS

9mA

3.3

Link Power Status (ISO-barrier supported)

SCLK

3.3

PHY Clock 49.152 MHz (ISO-barrier supported)

DIRECT

3.3

Auxiliary PHY/Link Signal is used to determine whether the

interconnection between Link and PHY has isolation (‘low’: ISO-

barrier; ‘high’: no ISO-barrier).

1.4 Serial ROM Interface Signals: (3 pins)

Name

I/O

Pin No.

IOL

Volts(V)

Function

GROM_SDA

I/O

6mA

3.3

Serial EEPROM Data Input / Output

GROM_SCL

6mA

3.3

Serial EEPROM Clock Output

GROM_EN

3.3

Serial EEPROM Enable (‘high’: GUID Load enabled; ‘low’: GUID

Load disabled)

1.5 Miscellaneous Signal: (1 pin)

Name

I/O

Pin No.

IOL

Volts(V)

Function

PIN_EN

5/3.3

Pin Enable Input (High clamped)

1.6 IC: (3 pins)

Name

I/O

Pin No.

IOL

Volts(V)

Function

IC(H)

3.3

Internally Connected (High clamped)

IC(L)

46, 47

3.3

Internally Connected (Low clamped)

1.7 NC: (5 pins)

Name

I/O

Pin No.

IOL

Volts(V)

Function

48, 49,

52, 53,

Non- Connection (Open)

Leave them unconnected.

1.8 VDD: (8 pins)

VDD (5 V PCI or 3.3 V PCI) for PCI I/Os: 11, 37, 92

VDD 3 V for digital core & PHY/Link I/Os: 1, 25, 51, 75, 97

1.9 VSS: (11 pins)

VSS : 6, 19, 26, 31, 38, 50, 63, 71, 76, 85, 100

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