Data Sheet S14265EJ2V0DS00

6

CONTENTS

1. PIN FUNCTIONS ..................................................................................................................................... 8

1.1 PCI Bus Interface Signals: (52 pins) .............................................................................................. 8

1.2 PCI/Cardbus Select Signals: (2 pins) ............................................................................................. 9

1.3 PHY/Link Interface Signals: (15 pins) .......................................................................................... 10

1.4 Serial ROM Interface Signals: (3 pins) ......................................................................................... 10

1.5 Miscellaneous Signal: (1 pin) ....................................................................................................... 10

1.6 IC: (3 pins) ...................................................................................................................................... 10

1.7 NC: (5 pins)..................................................................................................................................... 10

2. REGISTER DESCRIPTIONS................................................................................................................. 11

2.1 PCI Bus Mode Configuration Register ( CARD_ON=Low ) ........................................................ 11

2.1.1 Offset_00

VendorID Register .............................................................................................................12

2.1.2 Offset_02

DeviceID Register..............................................................................................................12

2.1.3 Offset_04

Command Register ............................................................................................................12

2.1.4 Offset_06

Status Register ..................................................................................................................13

2.1.5 Offset_08

Revision ID Register ..........................................................................................................14

2.1.6 Offset_09

Class Code Register..........................................................................................................14

2.1.7 Offset_0C

Cache Line Size Register..................................................................................................14

2.1.8 Offset_0D

Latency Timer Register .....................................................................................................14

2.1.9 Offset_0E

Header Type Register .......................................................................................................14

2.1.10 Offset_0F BIST Register ...................................................................................................................14

2.1.11 Offset_10

Base Address 0 Register .................................................................................................15

2.1.12 Offset_2C

Subsystem Vendor ID Register .......................................................................................15

2.1.13 Offset_2E

Subsystem ID Register....................................................................................................15

2.1.14 Offset_30

Expansion Rom Base Address Register..........................................................................15

2.1.15 Offset_34

Cap_Ptr Register .............................................................................................................15

2.1.16 Offset_3C

Interrupt Line Register.....................................................................................................16

2.1.17 Offset_3D

Interrupt Pin Register ......................................................................................................16

2.1.18 Offset_3E

Min_Grant Register .........................................................................................................16

2.1.19 Offset_3F

Max Lat Register .............................................................................................................16

2.1.20 Offset_40

PCI_OHCI_Control Register ............................................................................................16

2.1.21 Offset_60

Cap_ID & Next_Item_Ptr Register ...................................................................................17

2.1.22 Offset_62

Power Management Capabilities Register.......................................................................17

2.1.23 Offset_64

Power Management Control/Status Register...................................................................17

2.2 CardBus Mode Configuration Register ( CARD_ON=High ) ...................................................... 18

2.2.1 Offset_14/18

Base_Address_1/2 Register (CardBus Status Registers) ............................................19

2.2.2 Offset_28

Cardbus CIS Pointer..........................................................................................................20

2.2.3 Offset_80

CIS Area ............................................................................................................................20

3. SERIAL ROM INTERFACE.................................................................................................................. 21

3.1 Serial EEPROM Register ............................................................................................................... 21

3.2 Serial EEPROM Register Description .......................................................................................... 21

3.3 Load Control................................................................................................................................... 25

3.4 Programming Sequence Example................................................................................................ 25