AS3607 datasheet(51/71 Pages) AMSCO

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AS3606 AS3607 2v2

Data Sheet - R e g i s t e r D e f i n i t i o n

Table 38. Out_Cntr Register

Name

Base

Default

Out_Cntr

2-wire serial

00h

Offset: 1Ah-1

DCDC mode and XIRQ Output Control Register

This is an extended register and needs to be enabled by writing 001b to Reg. 1Ch first.

This register is reset at a VDD27-POR or XRES input.

Bit

Bit Name

Default

Access

Bit Description

DCDC23_1.4A

R/W

Combines DCDC2 and DCDC3 to one regulator for 1.4A output currents

0: DCDC2 and DCDC3 working independent

1: DCDC2 & DCDC3 combined for 1.4A (DCDC3 registers have no effect)

GPIO_HBN_ON

R/W

0: Hibernation enable via GPIOs disabled

1: Hibernation enalbe via GPIOs enabled

GPIO selected via GPIO_DIMM_HBN_SEL <1:0>

5:4

HBN_DELAY<1:0>

R/W

Sets the delay time for going into hibernation after writing to register 17-4h

00: 0ms

01: 8ms

10: 16ms

11: 32ms

3:2

DRIVE_XIRQ<1:0>

R/W

Sets the XIRQ output pin to open-drain, push-pull or tri-state and sets

various driving strengths

00: 6mA open-drain output

01: 6mA push-pull output

10: 1mA push-pull output

11: HiZ, tri-state

1:0

MUX_XIRQ<1:0>

R/W

Multiplexes various digital signals to the XIRQ output pin

00: XIRQ, active low interrupt request signal

01: CLKINT1, internal clock signal, see Clk_Cntr register

10: CLKINT2, internal clock signal, see Clk_Cntr register

11: IRQ, active low reset signal

Table 39. Clk_Cntr Register

Name

Base

Default

Clk_Cntr

2-wire serial

00h

Offset: 1Ah-2

Clock Control Register

This is an extended register and needs to be enabled by writing 010b to Reg. 1Ch first.

This register is reset at a VDD27-POR or XRES input.

Bit

Bit Name

Default

Access

Bit Description

7:6

CLKINT2<1:0>

R/W

Selects the CLKINT2 input source. Note, this is an internal clock, which can

be multiplexed to the XRES output.

00: LOW, drives the signal to logic “0”

01: CLK1Hz charger

10: do not use

11: HIGH, drives the signal to logic “1”

5:4

CLKINT1<1:0>

R/W

Selects the CLKINT1 frequency. Note, this is an internal clock, which can be

multiplexed to XIRQ output.

00: 2MHz

01: 1MHz

10: 1kHz

11: 125Hz

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