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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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AD9816JS Datasheet(PDF) 3 Page - Analog Devices |
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AD9816JS Datasheet(HTML) 3 Page - Analog Devices |
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3 / 16 page  –3– REV. A AD9816 DIGITAL SPECIFICATIONS (T MIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, DRVDD = +5.0 V, fADCCLK = 6 MHz, fCDSCLK1 = 2 MHz, fCDSCLK2 = 2 MHz, CL = 10 pF unless otherwise noted) Parameter Symbol Min Typ Max Units LOGIC INPUTS High Level Input Voltage VIH 3.5 V Low Level Input Voltage VIL 1.0 V High Level Input Current IIH 10 µA Low Level Input Current IIL 10 µA Input Capacitance CIN 10 pF LOGIC OUTPUTS High Level Output Voltage VOH 4.5 V Low Level Output Voltage VOL 0.1 V High Level Output Current IOH 50 µA Low Level Output Current IOL 50 µA Specifications subject to change without notice. TIMING SPECIFICATIONS (T MIN to TMAX with DVDD = +5.0 V, DRVDD = +5.0 V) Parameter Symbol Min Typ Max Units CLOCK PARAMETERS 3-Channel Conversion Rate tCRA 500 ns 1-Channel Conversion Rate tCRB 160 ns ADCCLK Pulsewidth tADCLK 80 ns CDSCLK1 Pulsewidth tC1 20 ns CDSCLK2 Pulsewidth tC2 60 2 tADCLK – 30 ns CDSCLK1 Falling to CDSCLK2 Rising tC1C2 5ns ADCCLK Falling to CDSCLK2 Rising tADC2 0ns CDSCLK2 Falling to ADCCLK Falling tC2AD 30 ns CDSCLK2 Falling to CDSCLK1 Rising tC2C1 10 ns Aperture Delay for CDS Clocks tAD 10 ns SERIAL INTERFACE Maximum SCLK Frequency fSCLK 10 MHz SLOAD to SCLK Set-Up Time tLS 10 ns SCLK to SLOAD Hold Time tLH 10 ns SDATA to SCLK Rising Set-Up Time tDS 10 ns SCLK Rising to SDATA Hold Time tDH 10 ns SCLK Falling to SDATA Valid tRDV 10 ns DATA OUTPUT Output Delay tOD 13 ns 3-State to Data Valid tDV 15 ns Output Enable High to 3-State tHZ 5ns Latency (Pipeline Delay) 3 (Fixed) ADCCLK Cycles |
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