AD9816

–9–

REV. A

period, and equal to one ADCCLK period minus 30 ns. The

output data latency is three ADCCLK cycles.

The offset and gain values for the red, green and blue channels

are programmed using the serial interface. The order in which

the channels are switched through the multiplexer is selected by

programming the MUX register. The rising edge of CDSCLK2

always resets the multiplexer.

1-Channel CDS Mode

This mode operates in the same way as the 3-channel CDS

mode. The difference is that the multiplexer remains fixed in

this mode, so only the channel specified in the MUX register is

processed. Because the AD9816 is still sampling all three chan-

nels, the unused inputs should be grounded through 1200 pF

capacitors.

Timing for this mode is shown in Figure 3, using a 3

× master

clock. Although it is not required, it is recommended that the

falling edge of CDSCLK2 be aligned with the rising edge of

ADCCLK.

1-Channel SHA Mode

This mode operates the same way as the 3-channel SHA mode,

except that the multiplexer remains stationary. Only the channel

specified in the MUX register is processed. Because the AD9816 is

still sampling all three channels, the unused inputs should be

grounded.

The input signal is sampled with respect to the voltage applied

to the OFFSET pin. With the OFFSET pin grounded, a zero

volt input corresponds to the ADC’s zero scale output. The

input clamp is disabled in this mode. However, the OFFSET

pin may be used as a coarse offset adjust pin. A voltage applied

to this pin will be subtracted from the voltages applied to the

red, green and blue inputs in the first amplifier stage of the

AD9816. For more information, see the Circuit Descriptions

section.

Timing for this mode is shown in Figure 4, using a 1

× master

clock. CDSCLK1 should be grounded in this mode of opera-

tion. Although it is not required, it is recommended that the

falling edge of CDSCLK2 be aligned with the rising edge of

ADCCLK.

Table I. Register Map

A2

A1

A0

Register

Power-On Default Value

0

0

0

Configuration Register

0 0 1 1 0 1 0 0 (LSB)

0

0

1

MUX Register

0 0 1 0 0 0 0 1 (LSB)

0

1

0

Red PGA Register

Undetermined

0

1

1

Green PGA Register

Undetermined

1

0

0

Blue PGA Register

Undetermined

1

0

1

Red Offset Register

Undetermined

1

1

0

Green Offset Register

Undetermined

1

1

1

Blue Offset Register

Undetermined

REGISTER OVERVIEW

The serial interface is used to program the eight internal regis-

ters of the AD9816. The address bits A2–A0 determine the

register in the AD9816 where serial data D7–D0 is written to or

read from.

The Configuration Register controls the operating mode of the

AD9816. Bits 7 (MSB), 6 and 0 are test mode bits and should

always be set to zero. Bit 5 is set high to enable the CDS mode.

Setting this bit low enables the SHA mode. Set Bit 4 high to

enable the 3 V input span. Set Bit 3 high to enable the 1.5 V

span. Bits 2 and 1 set the channel mode. Bit 2 enables 3-chan-

nel simultaneous sampling. Bit 1 enables single channel mode,

with the appropriate channel set in the MUX Register. At

power-on, this register defaults to 3-channel CDS mode with a

3 V input span, as shown in Table I.

7 6 5 4 3 2 1 0

TEST MODE (LSB)

1-CHANNEL MODE

3-CHANNEL MODE

1.5 V INPUT SPAN

3 V INPUT SPAN

CDS ENABLE

TEST MODE

TEST MODE (MSB)

Figure 7. Configuration Register

The MUX Register determines the order of channels that the

multiplexer will switch to in the different modes of operation.

Bit 7 and Bit 1 are test modes and should be set to zero. Bit 0 is

a test mode bit and should be set high. In 3-channel mode,

Table II shows how to set the order in which the channels are

converted. The multiplexer is always reset on the rising edge of

CDSCLK2. In 1-channel mode, the multiplexer is stationary,

and only converts the channel selected in Table III. At power-

on, this register defaults to 3-channel RGB mode.

7 6 5 4 3 2 1 0

TEST MODE (LSB)

TEST MODE

1-CHANNEL RED

1-CHANNEL GREEN

1-CHANNEL BLUE

3-CHANNEL BIT 0

3-CHANNEL BIT 1

TEST MODE (MSB)

Figure 8. MUX Register