AD9816

–13–

REV. A

Analog-to-Digital Converter

The AD9816 uses a high speed 12-bit ADC core. This CMOS

converter is designed to run at 6 MSPS with good linearity and

noise performance. Figure 19 shows the INL and DNL perfor-

mance of a typical AD9816 device, running at 6 MHz in 3-channel

CDS mode using the timing shown in Figure 1. The following

The digital outputs of the AD9816 follow a straight binary

coding scheme. Table VI shows the digital output coding for

the 3 V input span.

0.2

–1.6

0

4095

0.0

–0.2

–0.4

–0.6

–0.8

–1.2

–1.4

1200

400

1600

800

1.0

0.5

–1.0

1.5

2000

2400

2800

3200

3600

0.0

–0.5

0

4095

1200

400

1600

800

2000

2400

2800

3200

3600

MAX INL 0.18

MIN INL –1.46

MAX DNL 0.31

MIN DNL –0.33

Figure 19. Typical Linearity Performance

Table VI. Digital Output Format

Input Voltage

1

Digital Outputs

3.0 – 1 LSB

1111 1111 1111

3.0 – 2 LSB

1111 1111 1110

0.0 + 1 LSB

0000 0000 0001

0.0

0000 0000 0000

NOTE

CCD’s reference and data levels.

3:1

DIFF

MUX

RED

GREEN

BLUE

PGA

PGA

PGA

SELECT

MUX

CONTROL

2

ADCCLK

CDSCLK2

12-BIT ADC

PGAOUT_T

PGAOUT_C

Figure 17. PGA/MUX Circuit Configuration

ANALOG

INPUTS

CDSCLK2

ADCCLK

PGAOUT_T

PGAOUT_C

PIXEL n

BLUE

GREEN

RED

RESET

GREEN(n–1)

BLUE(n–1)

RED(n)

GREEN(n)

BLUE(n)

RESET

4.25V

3.5V

2.75V

Figure 18. PGA Output Voltages (ADC Input Range = 3 V)

Table V. Voltage Swing of PGA Outputs

Analog

Differential

Input

ADC

Voltage

1

PGAOUT_T

PGAOUT_C

Input

0.00

2

2.75

4.25

1.5

1.50

2

3.50

3.50

0.0

3.00

2

4.25

2.75

+1.5

0.00

3

3.125

3.875

0.75

0.75

3

3.50

3.50

0.0

1.50

3

3.875

3.125

+0.75

NOTES

ence and data levels.