AD9816

–14–

REV. A

APPLICATIONS INFORMATION

CDS Mode Circuit

The recommended circuit configuration for CDS mode opera-

tion is shown in Figure 20. The input coupling capacitor value

of 1200 pF is recommended, but this value may be adjusted to

suit a particular application (see Circuit Descriptions). A single

ground plane is recommended for the AD9816. A separate power

supply may be used for DRVDD, the digital driver supply, but this

AVDD

AVSS

CAPT

CAPT

CAPB

CAPB

VREF

CML

VINR

AVSS

VING

DRVSS

DB5

DB4

DB3

DB2

DB1

DB0 (LSB)

DVSS

SLOAD

SDATA

SCLK

AD9816

1

2

3

4

5

6

7

8

9

10

11

33

32

31

30

29

28

27

26

25

24

23

0.01 F

0.1 F

DB5

DB4

DB3

DB2

DB1

DB0 (LSB)

SLOAD

SDATA

SCLK

0.01 F

0.1 F

1200pF

1200pF

1200pF

RED_IN

GREEN_IN

BLUE_IN

1.0 F

+

0.1 F

10 F

+

10 F

0.1 F

0.1 F

0.1 F

0.01 F

0.1 F

0.1 F

0.01 F

ADCCLK

CDSCLK2

CDSCLK1

1k

0.1 F

1.0 F

1.5k

NC = NO CONNECT

Figure 20. Recommended Circuit for CDS Mode

supply pin should still be decoupled to the same ground plane

as the rest of the AD9816. The loading of the digital outputs

should be minimized, either by using short traces to the digital

ASIC, or by using external digital buffers. All 0.01

µF and

0.1

µF decoupling capacitors should be located as close as pos-

sible to the AD9816 pins. Also, the 1200 pF input capacitors

should be located close the AD9816’s analog input pins.