WM9093ECSSLASHR datasheet(18/84 Pages) WOLFSON

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WM9093

Production Data

PD, March 2012, Rev 4.2

INPUT PGA CONFIGURATION

The input PGAs can be configured in single-ended mode or differential mode, using the IN1_DIFF

and IN2_DIFF register bits described in Table 2.

In single-ended mode, an input pin is routed to each individual PGA. In differential mode, a pair of

input pins is routed to PGA IN1A or IN2A.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R22 (16h)

IN1 Line

Control

IN1_DIFF

PGA IN1A and IN1B configuration

0 = Single-ended mode

1 = Differential mode

R23 (17h)

IN2 Line

Control

IN2_DIFF

PGA IN2A and IN2B configuration

0 = Single-ended mode

1 = Differential mode

Table 2 Input PGA Configuration

INPUT PGA VOLUME CONTROL

Each of the four input PGAs has an independently controlled gain range of -6dB to +18dB. The gains

on the inverting and non-inverting inputs to the PGAs are always equal. Each Input PGA can be

independently muted using the PGA mute bits as described in Table 3.

Note that, in differential mode, PGA IN1B and/or IN2B is not used, and the volume control is provided

on IN1A only (for pins IN1+ and IN1-) or IN2A only (for pins IN2+ and IN2-).

Note also that in single-ended mode there is an additional +6dB gain which must be factored into the

volume control. For example a 0dB volume setting provides 0dB gain in differential mode, but in

single-ended mode it will apply +6dB gain. Therefore in single-ended mode the input PGAs have a

controlled gain range of 0dB to +24dB

To prevent “zipper noise”, a zero-cross function is provided on the input PGAs. When this feature is

enabled, volume updates will not take place until a zero-crossing is detected. In the case of a long

period without zero-crossings, a timeout function is provided. When the zero-cross function is

enabled, the volume will update after the timeout period if no earlier zero-cross has occurred. The

timeout clock is enabled using TOCLK_ENA, the timeout period is set by TOCLK_RATE. See

“Clocking Control” for more information on these fields.

The IN1_VU and IN2_VU bits control the loading of the input PGA volume data. When IN1_VU and

IN2_VU are set to 0, the PGA volume data will be loaded into the respective control register, but will

not actually change the gain setting. The IN1A and IN1B volume settings are both updated when a 1

is written to IN1_VU; the IN2A and IN2B volume settings are both updated when a 1 is written to

IN2_VU. This makes it possible to update the gain of two single-ended input paths simultaneously.

Note that, in differential input modes, the Volume Update control bits IN1_VU and/or IN2_VU should

always be set to 1.

The Input PGA Volume Control register fields are described in Table 3.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R24 (18h)

IN1 Line Input

A Volume

IN1_VU

N/A

IN1 Volume Update

Writing a 1 to this bit will cause IN1A and

IN1B input PGA volumes to be updated

simultaneously

IN1A_MUTE

IN1A PGA Mute

0 = Un-Mute

1 = Mute

IN1A_ZC

IN1A PGA Zero Cross Control

0 = Change gain immediately

1 = Change gain on zero cross only

WM9093ECS/R Datasheet(PDF) 18 Page - Wolfson Microelectronics plc

WM9093ECS/R Datasheet(HTML) 18 Page - Wolfson Microelectronics plc

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