WM9093ECSSLASHR datasheet(17/84 Pages) WOLFSON

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Production Data

WM9093

PD, March 2012, Rev 4.2

LINE INPUTS

All of the analogue input pins are designed as line inputs. Four of these pins (IN1+/- and IN2+/-) can

be configured as single-ended or differential inputs, with flexible routing options and gain controls

suitable for many different usage cases. The remaining inputs (IN3+ and IN3-) provide a low-power

signal path direct to the speaker output driver.

The line input pins IN1+ and IN1- provide a differential input path to PGA IN1A. These inputs provide

a high gain path if required for low input signal levels. If required, these input pins can be configured

as two separate single-ended inputs to PGAs IN1A and IN1B respectively. Single ended configuration

is selected by writing a 0 to the IN1_DIFF register bit.

The line input pins IN2+ and IN2- provide a differential input path to PGA IN2A. These inputs provide

a high gain path if required for low input signal levels. If required, these input pins can be configured

as two separate single-ended inputs to PGAs IN2A and IN2B respectively. Single ended configuration

is selected by writing a 0 to the IN2_DIFF register bit.

The line input pins IN3+ and IN3- provide a mono differential ‘voice bypass’ input (eg. From an

external voice CODEC) to the speaker drivers. This provides a low-power option, bypassing the input

and output mixer circuits.

Signal path configuration to the input PGAs is detailed later in this section. Signal path configuration

to the output mixers and speaker mixers is described in “Output Signal Path”.

Note that, by default, the analogue input pins are clamped to VMID in order to prevent audible pops

caused by enabling the input paths. When one or more analogue input path is in use, the respective

input clamp(s) must be disabled using the register bits described under “Power Sequences and Pop

Suppression Control”.

INPUT PGA ENABLE

The Input PGAs are enabled using register bits IN1A_ENA, IN1B_ENA, IN2A_ENA and IN2B_ENA,

as described in Table 1. The Input PGAs must be enabled for line input on the respective input pins.

Note that, for differential input on IN1+ and IN1-, it is not necessary to enable PGA IN1B.

Note that, for differential input on IN2+ and IN2-, it is not necessary to enable PGA IN2B.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (02h)

Power

Management

(2)

IN1A_ENA

IN1A Input PGA Enable

0 = Disabled

1 = Enabled

IN1B_ENA

IN1B Input PGA Enable

0 = Disabled

1 = Enabled

(Note this is only required for single-ended

input on the IN1- pin)

IN2A_ENA

IN2A Input PGA Enable

0 = Disabled

1 = Enabled

IN2B_ENA

IN2B Input PGA Enable

0 = Disabled

1 = Enabled

(Note this is only required for single-ended

input on the IN2- pin)

Table 1 Input PGA Enable

For normal operation of the input PGAs, the reference voltage VMID and the bias current must also

be enabled. See “Reference Voltages and Master Bias” for details of the associated controls

VMID_RES and BIAS_ENA.

WM9093ECS/R Datasheet(PDF) 17 Page - Wolfson Microelectronics plc

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