| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
910GL Datasheet(PDF) 154 Page - Intel Corporation |
|
|
|||||||||||||||||||||||||||||
910GL Datasheet(HTML) 154 Page - Intel Corporation |
|
154 / 426 page ![]() Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82915G/82915P/82915PL Only) R 154 Datasheet 8.1.36 LCAP—Link Capabilities (D1:F0) PCI Device: 1 Address Offset: ACh Default Value: 02012E01h Access: R/WO Size: 16 bits This register indicates PCI Express device specific capabilities. Bit Access & Default Description 31:24 RO 02h Port Number: This field indicates the PCI Express* port number for the given PCI Express link. This field matches the value in Element Self Description [31:24]. 23:18 Reserved 17:15 R/WO 010b L1 Exit Latency: This field indicates the length of time this Port requires to complete the transition from L1 to L0. The value 010 b indicates the range of 2 µs to less than 4 µs. If this field is required to be any value other than the default, BIOS must initialize it accordingly. Both bytes of this register that contain a portion of this field must be written simultaneously in order to prevent an intermediate (and undesired) value from ever existing. 14:12 R/WO 010b L0s Exit Latency: This field indicates the length of time this Port requires to complete the transition from L0s to L0. The value 010 b indicates the range of 128 ns to less than 256 ns. If this field is required to be any value other than the default, BIOS must initialize it accordingly. Note: When PCI Express* is operating with separate reference clocks, L0s exit latency may be greater than the setting in the L0s Exit Latency Register. Expect longer exit latency then setting in L0s Exit Latency Register. The link may enter Recovery state before reaching L0. System BIOS can program the appropriate Exit Latency and advertised N_FTS value if it detects that the downstream device is not using the common reference clock (indicated in the Slot Clock Configuration bit 12 of the device’s Link Status Register) 11:10 R/WO 11b Active State Link PM Support: L0s & L1 entry supported. 9:4 RO 10h Max Link Width: Hardwired to indicate X16. When Force X1 mode is enabled on this PCI Express* x16 Graphics Interface device, this field reflects X1 (01h). 3:0 RO 1h Max Link Speed: Hardwired to indicate 2.5 Gb/s. |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |