910GL datasheet(153/426 Pages) INTEL

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Host-PCI Express* Bridge Registers (D1:F0)

(Intel® 82915G/82915P/82915PL Only)

Datasheet

153

8.1.35

DSTS—Device Status (D1:F0)

PCI Device:

Address Offset:

AAh

Default Value:

0000h

Access:

Size:

16 bits

This register reflects status corresponding to controls in the Device Control register.

Note:

The error reporting bits are in reference to errors detected by this device, not errors messages

received across the link.

Bit

Access &

Default

Description

15:6

Reserved

Transactions Pending

0 = All pending transactions (including completions for any outstanding non-

posted requests on any used virtual channel) have been completed.

1 = Device has transaction(s) pending (including completions for any outstanding

non-posted requests for all used Traffic Classes).

Reserved

R/WC

Unsupported Request Detected:

1 = Device received an Unsupported Request. Errors are logged in this register

regardless of whether error reporting is enabled or not in the Device Control

R/WC

Fatal Error Detected:

1 = Fatal error(s) were detected. Errors are logged in this register regardless of

whether error reporting is enabled or not in the Device Control register.

R/WC

Non-Fatal Error Detected:

1 = Non-fatal error(s) were detected. Errors are logged in this register regardless

of whether error reporting is enabled or not in the Device Control register.

R/WC

Correctable Error Detected:

1 = Correctable error(s) were detected. Errors are logged in this register

regardless of whether error reporting is enabled or not in the Device Control

Note: The (G)MCH may report a false 8B/10B Receiver Error when exiting L0s.

This is reported thru the Correctable Error Detected bit CESTS device 1, offset

1D0h, Bit [0]. This will reduce the value of Receiver Error detection when L0s is

enabled. Disable L0s for accurate Receiver Error reporting.

910GL Datasheet(PDF) 153 Page - Intel Corporation

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