MC68HC705MC4MP datasheet(144/180 Pages) FREESCALE

144 / 180 page

Core Timer

MC68HC705MC4 — Rev. 2.0

Core Timer

12.5 Ctimer Counter Register

The core timer counter register is a read-only register that contains the

current value of the 8-bit ripple counter at the beginning of the timer

chain. This counter is clocked at fop divided by 4 and can be used for

various functions including a software input capture. Extended time

periods can be attained using the CTOF function to increment a

temporary RAM storage location, thereby simulating a 16-bit (or more)

counter.

The power-on cycle clears the entire counter chain and begins clocking

the counter. After 4064 cycles, the power-on reset circuit is released that

again clears the counter chain and allows the device to come out of

reset. At this point, if RESET is not asserted, the timer will start counting

up from zero and normal device operation will begin. When RESET is

asserted anytime during operation (other than POR), the counter chain

will be cleared.

12.6 Core Timer during Wait Mode

The CPU clock halts during wait mode, but the timer remains active. If

the interrupts are enabled, the timer interrupt will cause the processor to

exit wait mode.

Address:

$0009

Bit 7

654321

Bit 0

Read:

CTCR7

CTCR6

CTCR5

CTCR4

CTCR3

CTCR2

CTCR1

CTCR0

Write:

Reset:

11111111

Figure 12-3. Core Timer Counter Register (CTCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

MC68HC705MC4MP Datasheet(PDF) 144 Page - Freescale Semiconductor, Inc

MC68HC705MC4MP Datasheet(HTML) 144 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL