MC68HC705MC4MP datasheet(84/180 Pages) FREESCALE

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16-Bit Timer

MC68HC705MC4 — Rev. 2.0

16-Bit Timer

9.4 Output Compare

The output compare function may be used to generate an output

waveform and/or as an elapsed time indicator. If the TCMP/TCAP1 bit of

the TCR is set, output to the port pin is enabled. All of the bits in the

output compare register pair OCRH/OCRL are readable and writeable

and are not altered by the 16-bit timer’s control logic. Reset does not

affect the contents of these registers. See Figure 9-5.

The contents of the output compare registers are compared with the

contents of the free-running counter once every four internal clock

cycles. If a match is found, the output compare flag bit (OCF) is set and

the output level bit (OLVL) is clocked to the output latch. The values in

the output compare registers and output level bit should be changed

after each successful comparison to control an output waveform, or to

establish a new elapsed time-out. An interrupt can also accompany a

successful output compare if the output compare interrupt enable bit

(OCIE) is set.

After a CPU write cycle to the MSB of the output compare register pair

(OCRH), the output compare function is inhibited until the LSB (OCRL)

is written. Both bytes must be written if the MSB is written. A write made

only to the LSB will not inhibit the compare function. The free-running

Address:

$001D

Bit 7

654321

Bit 0

Read:

BIT 15

BIT 14

BIT 13

BIT 12

BIT 11

BIT 10

BIT 9

BIT 8

Write:

Reset:

Unaffected by Reset

Address:

$001E

Bit 7

654321

Bit 0

Read:

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Write:

Reset:

Unaffected by Reset

Figure 9-5. Output Compare Registers (OCRH/OCRL)

Freescale Semiconductor, Inc.

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