MC68HC705MC4MP datasheet(124/180 Pages) FREESCALE

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Serial Communications Interface

MC68HC705MC4 — Rev. 2.0

Serial Communications Interface

11.5.1.4 Idle Characters

An idle character contains all logic 1s and has no start or stop bits. Idle

character length depends on the M bit in SCCR1. The preamble is a

synchronizing idle character that begins every transmission.

Clearing the TE bit during a transmission relinquishes the PB4/TDO pin

after the last character to be transmitted is shifted out. The last character

may already be in the shift register, or waiting in the SCDR, or a break

character generated by writing to the SBK bit. Toggling TE from logic 0

to logic 1 while the last character is in transmission generates an idle

character (a preamble) that allows the receiver to maintain control of the

PB4/TDO pin.

11.5.1.5 Transmitter Interrupts

All SCI interrupt sources share the same interrupt vector at address

$0FF2. The following sources can generate SCI transmitter interrupt

requests:

•

Transmit Data Register Empty (TDRE) — The TDRE bit in the

SCSR indicates that the SCDR has transferred a character to the

transmit shift register. TDRE is a source of SCI interrupt requests.

The transmission interrupt enable bit (TIE) in SCCR2 is the local

mask for TDRE interrupts.

•

Transmission Complete (TC) — The TC bit in the SCSR indicates

that both the transmit shift register and the SCDR are empty and

that no break or idle character has been generated. TC is a source

of SCI interrupt requests. The transmission complete interrupt

enable bit (TCIE) in SCCR2 is the local mask for TC interrupts.

11.5.2 Receiver

Figure 11-3 shows the structure of the SCI receiver.

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MC68HC705MC4MP Datasheet(PDF) 124 Page - Freescale Semiconductor, Inc