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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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ADRF6655ACPZ-R7 Datasheet(PDF) 24 Page - Analog Devices |
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ADRF6655ACPZ-R7 Datasheet(HTML) 24 Page - Analog Devices |
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24 / 44 page  ADRF6655 Rev. 0 | Page 24 of 44 REGISTER STRUCTURE DIVIDE MODE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 00 00 00 000 00 00 DM ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0) INTEGER DIVIDE RATIO CONTROL BITS RESERVED INTEGER DIVIDE CONTROL REGISTER (R0) MODULUS DIVIDE CONTROL REGISTER (R1) MODULUS DIVIDE VALUE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 MD10 MD9 MD8 MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 C3(0) C2(0) C1(1) CONTROL BITS RESERVED FRACTIONAL DIVIDE CONTROL REGISTER (R2) FRACTIONAL DIVIDE VALUE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 0 0 0 0 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 C3(0) C2(1) C1(0) CONTROL BITS RESERVED Σ-Δ MODULATOR DITHER CONTROL REGISTER (R3) DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 DITH1 DITH0 DEN C3(0) C2(1) C1(1) CONTROL BITS DITHER ENABLE DV16 DV15 DV14 DV13 DV12 DV11 DV10 DV9 DV8 DV7 DV6 DV5 DV4 DV3 DV2 DV1 DV0 DITHER MAGNITUDE DITHER RESTART VALUE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 XVCO 0 0 C3(1) C2(1) C1(1) CONTROL BITS 00 00 00 00 00 00 000 00 EXTERNAL VCO ENABLE RESERVED CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL REGISTER (R4) CP REF PDF PHASE OFFSET POLARITY CP CNTL SRC DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RMS2 RMS1 RMS0 RS1 RS0 CPM CPBD CPB4 CPB3 CPB2 CPB1 CPB0 CPP1 CPP0 CPS CPC1 CPC0 PE1 PE0 PAB1 PAB0 C3(1) C2(0) C1(0) OUPUT MUX SOURCE INPUT REF PATH SOURCE PFD PHASE OFFSET MULTIPLIER VALUE CP CURRENT MULTIPLIER CHARGE PUMP CONTROL PFD EDGE SENSITIVITY CONTROL BITS PFD ANTI- BACKLASH DELAY LO PATH AND MIXER CONTROL REGISTER (R5) RESERVED MIXER BIAS ENABLE PLL ENABLE LO DIV 2/3 LO IN/OUT CNTRL LO OUTPUT DRIVER ENABLE DB23DB22DB21DB20DB19DB18DB17DB16DB15DB14 DB13 DB12 DB7 MBE DB6 DB5 DB4 DB3 DB11 CDAC3 DB10 CDAC2 DB9 CDAC1 DB8 CDAC0 PLEN LDIV LXL LDRV CDAC DISTORTION COMPENSATION SETTING CONTROL BITS 00 0 0 0 000 00 0 0 VCO CONTROL AND PLL ENABLES REGISTER (R6) DB2 DB1 DB0 C3(1) C2(0) C1(1) CONTROL BITS DB2 DB1 DB0 C3(1) C2(1) C1(0) CHARGE PUMP ENABLE LDO 3.3V ENABLE VCO ENABLE VCO SWITCH CONTROL VCO BS SRC VCO LDO ENABLE VCO AMPLITUDE SETTING RESERVED VCO BAND SELECT DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB23 CPEN L3EN VCOEN VCOSW VC5 VC4 VC3 VC2 VC1 VC0 VBSRC VBS5 VBS4 VBS3 VBS2 VBS1 VBS0 LVEN 000 EXTERNAL VCO CONTROL REGISTER (R7) RES Figure 69. Register Maps for ADRF6655 (The three control bits determine which register is programmed.) |
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