ADRF6655ACPZ-R7 datasheet(31/44 Pages) AD

31 / 44 page

ADRF6655

Rev. 0 | Page 31 of 44

With R5[2:0] set to 101, the LO path and mixer control register

is programmed as shown in Figure 75.

The LO output driver can be enabled to allow the user to review

the performance of the internally applied LO through the LOP

and LON local oscillator input/output pins. The LO input/output

control allows the user to disconnect the internal LO signal and

apply an external LO signal to the LOP and LON local oscillator

input/output pins. A divide-by-2 or divide-by-3 prescaler can be

selected to divide the frequency of the externally or internally

applied oscillator signal before the mixer.

When using an external frequency, stable local oscillator signal

to commutate the mixer core, it is possible to shut down the PLL

circuitry through the PLL enable address (DB6) of Register 5.

The internal mixer can be disabled using the mixer bias enable

address (DB7) of Register 5.

Compensation Setting (DB11:DB8). CDAC control can allow

the user to optimize the internal linearization circuitry to enhance

IP3 performance for high frequency RF input signals.

CDAC3 CDAC2 CDAC1 CDAC0

MINIMUM

...

MAXIMUM

CDAC DISTORTION

COMPENSATION

SETTLING

LDRV

LO OUTPUT DRIVER

ENABLE

DRIVER OFF (RECOMMENDED)

DRIVER ON

LXL

LO IN/OUT CONTROL

LO OUTPUT

LO INPUT

LDIV

DIVIDE BY 3

DIVIDE BY 2

DIVIDE-BY-2 OR DIVIDE-BY-3

PLEN

DISABLE

ENABLE

PLL ENABLE

MBE

DISABLE

ENABLE

MIXER BIAS ENABLE

RESERVED

MIXER

BIAS

ENABLE

PLL

ENABLE

DIV 2/3

IN/OUT

CNTRL

LO OUTPUT

DRIVER

ENABLE

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12

DB7

MBE

DB6

DB5

DB4

DB3

DB11

CDAC3

DB10

CDAC2

DB9

CDAC1

DB8

CDAC0

PLEN

LDIV

LXL

LDRV

CDAC DISTORTION

COMPENSATION

SETTING

CONTROL BITS

00000

000

DB2

DB1

DB0

C3(1) C2(0) C1(1)

Figure 75. LO Path and Mixer Control Register (R5)

ADRF6655ACPZ-R7 Datasheet(PDF) 31 Page - Analog Devices

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