LTC2402 datasheet(22/32 Pages) LINER

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LTC2401/LTC2402

used to shift the conversion result into external circuitry.

After the 32nd rising edge, CS is pulled HIGH and a new

conversion is immediately started. This is useful in appli-

cations requiring periodic monitoring and ultralow power.

Figure 14 shows the average supply current as a function

of capacitance on CS.

It should be noticed that the external capacitor discharge

current is kept very small in order to decrease the con-

verter power dissipation in the sleep state. In the autostart

mode the analog voltage on the CS pin cannot be observed

without disturbing the converter operation using a regular

oscilloscope probe. When using this configuration, it is

important to minimize the external leakage current at the

CS pin by using a low leakage external capacitor and

properly cleaning the PCB surface.

The internal serial clock mode is selected every time the

voltage on the CS pin crosses an internal threshold volt-

age. An internal weak pull-up at the SCK pin is active while

CS is discharging; therefore, the internal serial clock

timing mode is automatically selected if SCK is floating. It

is important to ensure there are no external drivers pulling

SCK LOW while CS is discharging.

as 100

µs. However, some considerations are required to

take advantage of exceptional accuracy and low supply

current.

The digital output signals (SDO and SCK in Internal SCK

mode of operation) are less of a concern because they are

not generally active during the conversion state.

In order to preserve the LTC2401/LTC2402’s accuracy, it

is very important to minimize the ground path impedance

which may appear in series with the input and/or reference

signal and to reduce the current which may flow through

this path. The GND pin should be connected to a low

resistance ground plane through a minimum length trace.

The use of multiple via holes is recommended to further

reduce the connection resistance.

In an alternative configuration, the GND pin of the converter

can be the single-point-ground in a single point grounding

system. The input signal ground, the reference signal

ground, the digital drivers ground (usually the digital

ground) and the power supply ground (the analog ground)

should be connected in a star configuration with the com-

mon point located as close to the GND pin as possible.

The power supply current during the conversion state

should be kept to a minimum. This is achieved by restrict-

ing the number of digital signal transitions occurring

during this period.

While a digital input signal is in the range 0.5V to

(VCC – 0.5V), the CMOS input receiver draws additional

current from the power supply. It should be noted that,

when any one of the digital input signals (FO, CS and SCK

in External SCK mode of operation) is within this range, the

LTC2401/LTC2402 power supply current may increase

even if the signal in question is at a valid logic level. For

micropower operation and in order to minimize the poten-

tial errors due to additional ground pin current, it is

recommended to drive all digital input signals to full CMOS

levels [VIL < 0.4V and VOH > (VCC – 0.4V)].

Severe ground pin current disturbances can also occur

due to the undershoot of fast digital input signals. Under-

shoot and overshoot can occur because of the impedance

mismatch at the converter pin when the transition time of

an external control signal is less than twice the propaga-

tion delay from the driver to LTC2401/LTC2402. For

APPLICATIO S I FOR ATIO

CAPACITANCE ON CS (pF)

100

150

200

250

300

100

1000

10000

24012 F14

100000

VCC = 5V

VCC = 3V

Figure 14. CS Capacitance vs Supply Current

DIGITAL SIGNAL LEVELS

The LTC2401/LTC2402’s digital interface is easy to use.

Its digital inputs (FO, CS and SCK in External SCK mode of

operation) accept standard TTL/CMOS logic levels and the

internal hysteresis receivers can tolerate edge rates as slow

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