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LTC2402 Datasheet(PDF) 16 Page - Linear Technology

No. de pieza LTC2402
Descripción Electrónicos  1-/2-Channel 24-Bit mPower No Latency DSTMADCs in MSOP-10
PDF  32 Pages
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Fabricante Electrónico  LINER [Linear Technology]
Página de inicio  http://www.linear.com
Logo LINER - Linear Technology

LTC2402 Datasheet(HTML) 16 Page - Linear Technology

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LTC2401/LTC2402
Figure 5. External Serial Clock, Single Cycle Operation
APPLICATIO S I FOR ATIO
EOC
BIT 31
SDO
SCK
(EXTERNAL)
CS
TEST EOC
MSB
SUB LSB
EXR
CH0/CH1
BIT 0
LSB
BIT 4
BIT 27
BIT 26
BIT 28
BIT 29
BIT 30
SLEEP
DATA OUTPUT
CONVERSION
24012 F05
CONVERSION
Hi-Z
Hi-Z
Hi-Z
TEST EOC
TEST EOC
VCC
FO
FSSET
ZSSET
SCK
CH1
SDO
GND
CS
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
0V TO FSSET – 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1
µF
110
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2402
VCC
3-WIRE
SERIAL I/O
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
SDO
SCK
(EXTERNAL)
CS
DATA OUTPUT
CONVERSION
SLEEP
SLEEP
TEST EOC
TEST EOC
DATA OUTPUT
Hi-Z
Hi-Z
Hi-Z
CONVERSION
24012 F06
MSB
EXR
SIG
CH0/CH1
BIT 8
BIT 27
BIT 9
BIT 28
BIT 29
BIT 30
EOC
BIT 31
BIT 0
EOC
Hi-Z
TEST EOC
VCC
FO
FSSET
ZSSET
SCK
CH1
SDO
GND
CS
REFERENCE VOLTAGE
ZSSET + 0.1V TO VCC
0V TO FSSET – 100mV
CH0
= INTERNAL OSC/50Hz REJECTION
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/60Hz REJECTION
1
µF
110
9
8
7
6
2
3
4
5
2.7V TO 5.5V
LTC2402
VCC
3-WIRE
SERIAL I/O
ANALOG INPUT RANGE
ZSSET – 0.12VREF TO
FSSET + 0.12VREF
(VREF = FSSET – ZSSET)
Figure 6. External Serial Clock, Reduced Data Output Length



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