LTC2402 datasheet(14/32 Pages) LINER

14 / 32 page

LTC2401/LTC2402

external serial clock. If the change occurs during the

conversion state, the result of the conversion in progress

may be outside specifications but the following conver-

sions will not be affected. If the change occurs during the

data output state and the converter is in the Internal SCK

mode, the serial clock duty cycle may be affected but the

serial data stream will remain valid.

Table 3 summarizes the duration of each state as a

function of FO.

SERIAL INTERFACE

The LTC2401/LTC2402 transmit the conversion results

and receives the start of conversion command through a

synchronous 3-wire interface. During the conversion and

sleep states, this interface can be used to assess the

converter status and during the data output state it is used

to read the conversion result.

Serial Clock Input/Output (SCK)

The serial clock signal present on SCK (Pin 9) is used to

synchronize the data transfer. Each bit of data is shifted out

the SDO pin on the falling edge of the serial clock.

In the Internal SCK mode of operation, the SCK pin is an

output and the LTC2401/LTC2402 create their own serial

clock by dividing the internal conversion clock by 8. In the

External SCK mode of operation, the SCK pin is used as

input. The internal or external SCK mode is selected on

power-up and then reselected every time a HIGH-to-LOW

transition is detected at the CS pin. If SCK is HIGH or float-

ing at power-up or during this transition, the converter

enters the internal SCK mode. If SCK is LOW at power-up

or during this transition, the converter enters the external

SCK mode.

Serial Data Output (SDO)

The serial data output pin, SDO (Pin 8), drives the serial

data during the data output state. In addition, the SDO pin

is used as an end of conversion indicator during the

conversion and sleep states.

When CS (Pin 7) is HIGH, the SDO driver is switched to a

high impedance state. This allows sharing the serial

interface with other devices. If CS is LOW during the

convert or sleep state, SDO will output EOC. If CS is LOW

during the conversion phase, the EOC bit appears HIGH on

the SDO pin. Once the conversion is complete, EOC goes

LOW. The device remains in the sleep state until the first

rising edge of SCK occurs while CS = 0.

Chip Select Input (CS)

The active LOW chip select, CS (Pin 7), is used to test the

conversion status and to enable the data output transfer as

described in the previous sections.

Table 3. LTC2401/LTC2402 State Duration

State

Operating Mode

Duration

CONVERT

Internal Oscillator

FO = LOW

133ms

(60Hz Rejection)

FO = HIGH

160ms

(50Hz Rejection)

External Oscillator

FO = External Oscillator

20510/fEOSCs

with Frequency fEOSC kHz

(fEOSC/2560 Rejection)

SLEEP

As Long As CS = HIGH Until CS = 0 and SCK

DATA OUTPUT

Internal Serial Clock

FO = LOW/HIGH

As Long As CS = LOW But Not Longer Than 1.67ms

(Internal Oscillator)

(32 SCK cycles)

FO = External Oscillator with

As Long As CS = LOW But Not Longer Than 256/fEOSCms

Frequency fEOSC kHz

(32 SCK cycles)

External Serial Clock with

As Long As CS = LOW But Not Longer Than 32/fSCKms

Frequency fSCK kHz

(32 SCK cycles)

APPLICATIO S I FOR ATIO

LTC2402 Datasheet(PDF) 14 Page - Linear Technology

LTC2402 Datasheet(HTML) 14 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Descarga

Enlace URL