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STLS2F02 Datasheet(PDF) 36 Page - STMicroelectronics

No. de pieza STLS2F02
Descripción Electrónicos  Loongson 2F high performance 64-bit superscalar MIPS® microprocessor
PDF  49 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLS2F02 Datasheet(HTML) 36 Page - STMicroelectronics

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DDR2 SDRAM controller interface description
STLS2F02
36/49
4.5
DDR2 SDRAM sample mode configuration
A DDR2 SDRAM controller is integrated in the STLS2F02. A delay compensation circuit
(using a DLL) samples return data on DQS. Since there is a data return path delay between
the memory controller and the SDRAM module, it is necessary to introduce a set of control
signals to measure the delay.
The control signals of DDR2_GATE_I[3:0] and DDR2_GATE_O[3:0] are used for the delay
measurement. On the PCB the signals DDR2_GATE_I and DDR2_GAT_O are connected
together to imitate the wiring delay on the PCB. The sampling accuracy is thus guaranteed.



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