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STLS2F02 Datasheet(PDF) 28 Page - STMicroelectronics

No. de pieza STLS2F02
Descripción Electrónicos  Loongson 2F high performance 64-bit superscalar MIPS® microprocessor
PDF  49 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLS2F02 Datasheet(HTML) 28 Page - STMicroelectronics

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DDR2 SDRAM controller interface description
STLS2F02
28/49
OUT_OF_RANGE_TYPE
42:40
0x0
0x0-0x7
Type of cmd that caused and Out-of-
Range interrupt. READ-ONLY
MAX_CS_REG
34:32
0x4
0x0-0x4
Maximum number of chip selects
available. READ-ONLY
CONF_CTL_06[31:0]
Offset: 0x60
DDR2 667:0x03040203
TRTP
26:24
0x0
0x0-0x7
DRAM TRTP parameter in cycles.
TRRD
18:16
0x0
0x0-0x7
DRAM TRRD parameter in cycles.
TEMRS
10:8
0x0
0x0-0x7
DRAM TEMRS parameter in cycles.
TCKE
2:0
0x0
0x0-0x7
Minimum CKE pulse width.
CONF_CTL_06[63:32]
Offset: 0x60
DDR2 667:0x0a040305
APREBIT
59:56
0x0
0x0-0xF
Location of the auto pre-charge bit in
the DRAM address.
WRLAT
50:48
0x0
0x0-0x7
DRAM WRLAT parameter in cycles.
TWTR
42:40
0x0
0x0-0x7
DRAM TWTR parameter in cycles.
TWR_INT
34:32
0x0
0x0-0x7
DRAM TWR parameter in cycles.
CONF_CTL_07[31:0]
Offset: 0x70
DDR2 667:0x000F090A
ECC_C_ID
27:24
0x0
0x0-0xF
Source ID associated with correctable
ECC event. READ-ONLY
CS_MAP
19:16
0x0
0x0-0xF
Number of active chip selects used in
address decoding.
CASLAT_LIN_GATE
11:8
0x0
0x0-0xF
Adjusts data capture gate open by half
cycles.
CASLAT_LIN
3:0
0x0
0x0-0xF
Sets latency from read cmd send to
data receive from/to controller.
CONF_CTL_07[63:32]
Offset: 0x70
DDR2 667:0x00000400
MAX_ROW_REG
59:56
0xF
0x0-0xF
Maximum width of memory address
bus. READ-ONLY
MAX_COL_REG
51:48
0xE
0x0-0xe
Maximum width of column address in
DRAMs. READ-ONLY
INITAREF
43:40
0x0
0x0-0xF
Number of auto-refresh cmds to
execute during DRAM initialization.
ECC_U_ID
35:32
0x0
0x0-0xF
Source ID associated with the
uncorrectable ECC even. READ-ONLY
CONF_CTL_08[31:0]
Offset: 0x80
DDR2 667:0x01020408
ODT_RD_MAP_CS3
27:24
0x0
0x0-0xF
ODT chip select 3 map for reads.
Determines which chip(s) have
termination when a read occurs on chip
3.
Table 12.
DDR SDRAM configuration parameter register format (continued)
Parameters
Bits
Default
value
Range
Description



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