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STLS2F02 Datasheet(PDF) 25 Page - STMicroelectronics

No. de pieza STLS2F02
Descripción Electrónicos  Loongson 2F high performance 64-bit superscalar MIPS® microprocessor
PDF  49 Pages
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Fabricante Electrónico  STMICROELECTRONICS [STMicroelectronics]
Página de inicio  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STLS2F02 Datasheet(HTML) 25 Page - STMicroelectronics

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STLS2F02
DDR2 SDRAM controller interface description
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4.4.3
Parameter formats
Table 12.
DDR SDRAM configuration parameter register format
Parameters
Bits
Default
value
Range
Description
CONF_CTL_00[31:0] Offset: 0x00
DDR2 667:0x00000101
AREFRESH
24:24
0x0
0x0-0x1
Initiate auto-refresh when specified by
AUOT_REFRESH_MODE. WRITE-
ONLY
AP
16:16
0x0
0x0-0x1
Enable auto pre-charge mode of
controller
ADDR_CMP_EN
8:8
0x0
0x0-0x1
Enable address collision detection for
command queue placement logic
ACTIVE_AGING
0:0
0x0
0x0-0x1
Enable command aging in the
command queue, avoiding low priority
command hungry
CONF_CTL_00[63:32] Offset: 0x00
DDR2 667:0x01000100
DDR2_SDRAM_MODE
56:56
0x0
0x0-0x1
DDRI or DDRII mode
CONCURRENTAP
48:48
0x0
0x0-0x1
Allow controller to issue cmds to other
banks while a bank is in auto pre-
charge. Note: most DDR2 DIMM
vendor do not support this feature
BANK_SPLIT_EN
40:40
0x0
0x0-0x1
Enable bank splitting for cmd queue
placement logic
AUTO_REFRESH_MODE
32:32
0x0
0x0-0x1
Sets if auto-refresh occurs be at next
burst or next cmd boundary
CONF_CTL_01[31:0] Offset: 0x10
DDR2 667:0x00010000
ECC_DISBALE_W_UC_ERR
24:24
0x0
0x0-0x1
Disable auto-corruption of ECC when
un-correctable errors occur in R/M/W
operations.
DQS_N_EN
16:16
0x0
0x0-0x1
Single-ended or differential dqs pins.
DLL_BYPASS_MODE
8:8
0x0
0x0-0x1
Enable the DLL bypass feature of the
controller.
DLLLOCKREG
0:0
0x0
0x0-0x1
Status of DLL lock coming out of
master delay. READ-ONLY
CONF_CTL_01[63:32] Offset: 0x10
DDR2 667:0x00100000
FWC
56:56
0x0
0x0-0x1
Force a write checks. Xor
XOR_CHECK_BITS with ecc code and
write to memory. WRITE_ONLY
FAST_WRITE
48:48
0x0
0x0-0x1
Sets when write cmds are issued to
DRAM device.
ENABLE_QUICK_SREFRESH
40:40
0x0
0x0-0x1
Allows user to interrupt memory
initialization to enter self-refresh mode.
EIGHT_BANK_MODE
32:32
0x0
0x0-0x1
Number of banks on the DRAM(s).



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