ORSPI4 datasheet(24/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

ORSPI4 SPI4 Data Formats

The data format across the SPI4 interface follows the OIF SPI4 convention where the lowest byte number occupies

the highest bit positions within the 16-bit word as shown in Figure 5. On payload transfers that do not end on an

even byte boundary, the unused byte (after the last valid byte) on bit positions 7 through 0 is set to all zeroes as

shown in Figure 5.

Figure 5. SPI4 Byte and Bit Ordering

At the FPGA-embedded core RX and TX interface, the same SPI4 convention is followed wherein the lowest byte

number occupies the highest bit positions within a word. This is the same in all operating modes - 32-bit, 64-bit and

128-bit.

Byte enables for all data except EOP should be “1”. During an EOP, the last valid byte enable within a 32-bit, 64-bit

or 128-bit word indicates the last byte for the packet. Figure 6 shows EOP signal being asserted during Word 3. In

Figure 6, the last valid byte enable within “1110” in Word 3 indicates the EOP. The valid byte enables during an

EOP are “1111”, “1110”, “1100” and “1000”. If the packet was errored, the ERR signal is asserted and will remain

asserted until EOP as shown in Figure 6

Figure 6. Example of EOP Indication in 32-Bit Mode

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

x (set to zeros)

Byte 0

Byte 1

Byte 2

Byte 3

Byte 4

x (set to zeros)

TDAT

RDAT

Word 0

Word 1

Word 2

Word 3

0 123

Byte

Bit

BE0

BE1

BE2

BE3

1 1

1 0

SPI[A,B]_TX32_EOP_j

Clock 1

Clock 2

Clock 3

Clock 4

SPI[A,B]_TX32_ERR_j

SPI[A,B]_RX32_EOP_j

SPI[A,B]_RX32_ERR_j

ORSPI4 Datasheet(PDF) 24 Page - Lattice Semiconductor

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