ORSPI4 datasheet(42/263 Pages) LATTICE

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Lattice Semiconductor

ORCA ORSPI4 Data Sheet

• The SOP must always be written into the ﬁrst byte location of the 16-byte DPRAM word. (Shown in Figure 7 for

the 32-bit interface mode.) With the Lattice SPI4 interface, the EOP may occur during any of the four 4-byte

mode writes to ﬁll the 16-byte DPRAM, and will be associated with the correct 128-bit line within the partition

memory.

The next two ﬁgures show the 64-bit write protocol from the FPGA to the TX DPRAMs. It is functionally identical to

the 32-bit mode, except two writes are required to ﬁll an address line within a FIFO partition instead of four. Figure

13 shows the basic interface signals for 64-bit mode of operation.

Figure 13. Basic 64-Bit Data Write Protocol to DPRAM

During Clock cycle 1, the FPGA asserts the partition Address, which indicates which partition within the DPRAM

the data and control signals are to be written to. The Write Enable signal is also asserted, qualifying all data and

control signals. From the ﬁgure, this is the start of a packet, so the SOP signal is also asserted. Data is presented

to the interface, as well as the Byte Enable (BE) and Port ID signals. The BE vector is used to qualify which Bytes

on the SPI4 transmit link are valid data. When operating in 64-bit mode, there are 8 BE bits. During clock cycle 6

the BE bits are set to 0xFE, indicating 7 of the eight Bytes contain valid packet data.

As with 32-bit mode, the Port ID signal should be asserted during an entire write sequence, although as a minimum

it must be asserted at least during the second write to the current DPRAM address line. In the ﬁgure above, the

Port ID must be asserted during clock cycles 2, 4, and 6.

During clock cycle 6, the FPGA indicates an End of Packet condition for the current selected Port. Asserting the

EOP signal causes the internal logic to terminate writes to the current Port. Also, the internal DPRAM pointer logic

is advanced after every second write to the DPRAM when in 64-bit aggregation mode.

As with the 32-bit aggregation mode, the “internal DPRAM Write Ptr” advances to the next valid address within par-

tition range, but after every 2 writes when in 64-bit aggregation mode. This is because two 64-bit writes ﬁll an entire

128-bit DPRAM line entry. The same interface logic in the FPGA can also be used as described in 32-bit mode, but

the counter implemented in FPGA logic is simply a one-bit toggle FF.

SPIA_TX64_CLK

SPIA_TX64_WD_CNT_RST

345

SPIA_TX64_ADDR[2:0]

SPIA_TX64_WE

SPIA_TX64_DATA[63:0]

SPIA_TX64_SOP

SPIA_TX64_EOP

SPIA_TX64_PORT[7:0]

SPIA_TX64_BE[7:0]

Note SPIB is identical to SPIA

Port 3

0xFF

0xFE

0xFF

Partition Addr 'k'

Port 3

ORSPI4 Datasheet(PDF) 42 Page - Lattice Semiconductor

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