ORSPI4 datasheet(52/263 Pages) LATTICE

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ORCA ORSPI4 Data Sheet

Figure 19. Transmit Calendar Control Logic Functional Diagram

The Transmit SPI4 interface contains both main and shadow Calendars enabling a hitless switch over between an

old and new Calendar schedule. Each Calendar is 1023 locations deep, providing a high degree of ﬂexibility and

customizable port service algorithms. The user can conﬁgure the Calendar(s) through software conﬁguration regis-

ters. (See the transmit memory map register set for identiﬁcation of individual conﬁguration register addresses).

NOTE, in order to effect a hitless switch at the logical port level, the user must ensure that port data associated with

any Calendar modiﬁcations have been terminated correctly before the Calendar switches. For example, if the

Shadow Calendar eliminates Port 3 from the Calendar sequence, the user must ensure there is no data associated

for Port 3 in the FIFO partitions when the Calendar switches. Otherwise, service will be granted for an out-of-ser-

vice port, causing higher layer protocol exceptions.

The Calendar length is also conﬁgurable to indicate the number of valid port entries. Programming the

CALENDAR_LEN register indicates how many entries within the Transmit Calendar are enabled for sequencing.

Since the Calendar is 1023 locations deep, a single port may be serviced more than once per Calendar sequence.

Port Service Information

The TCC sequentially runs through the Calendar sequence retrieving the port number that is to be serviced next.

The ﬁeld is an 8-bit vector, supporting the entire 256 possible entries of the SPI4 Calendar. The retrieved port num-

ber is used to index a Port Descriptor Memory (PDM) to retrieve all pertinent information required for maintaining

proper port servicing.

There are several ﬁelds within the PDM that are required to be conﬁgured by the user before the Transmit interface

can be enabled. A description of the ﬁelds within the descriptor is given below:

• PORT_ID - Port information sent to the FPGA when a port is being serviced. This value is conﬁgurable by the

user and can contain either the SPI4 number of the port, or can contain an alias the FPGA uses to map propri-

etary interface channels to the corresponding SPI4 port (See the 'M'-bit description below). The FPGA logic can

also use the Port_ID for status acquisition, or other link layer ﬂow control functions. After reset this ﬁeld defaults

to a value of 8'h00.

• BURST_VAL - Port information sent to the FPGA (when a port is being serviced) and AMA. This user-conﬁg-

urable ﬁeld indicates the maximum number of 16-Byte burst accesses the port is permitted to consecutively

transmit across the SPI4 link, before segmentation must be performed. The FPGA can use this ﬁeld to indicate

how much data to source for the port being polled to maintain buffering within the DPRAM FIFO partition. After

reset this ﬁeld defaults to a value of 4'h0.

SPI[A,B]_TX_STAT

Transmit

Calendar

Main/

SPI[A,B]_TX_PORT_ID

BURST_VAL

AMA_ID

255

CREDIT

BURST_VAL

Port Seq Addr

Port Desc Data

STATUS

UPDATE

LOGIC

PORT_ID

PORT_STAT

SPI[A,B]_TX_BURST_VAL

Shadow

MB_EN M

PORT_ID

STATUS

AMA

BANK_ID

PARTITION_ID

Port

Memory

Descriptor

ORSPI4 Datasheet(PDF) 52 Page - Lattice Semiconductor

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