ADMV4530 datasheet(2/64 Pages) AD

2 / 64 page

Data Sheet

ADMV4530

TABLE OF CONTENTS

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Rev. C | 2 of 64

Features................................................................ 1

Applications........................................................... 1

General Description...............................................1

Functional Block Diagram......................................3

Specifications........................................................ 4

I/Q Mode ............................................................5

IF Mode.............................................................. 6

Absolute Maximum Ratings...................................7

Thermal Information........................................... 7

ESD Caution.......................................................8

Pin Configuration and Function Descriptions........ 9

Typical Performance Characteristics................... 11

I/Q Mode...........................................................11

IF Mode ........................................................... 17

Return Loss and Leakages.............................. 22

VCO and PLL .................................................. 25

Upconverter M × N Spurious Performance...... 29

Theory of Operation.............................................30

SPI Configuration............................................. 30

Double Buffered Registers............................... 30

Start-Up Initialization Sequence....................... 30

Frequency Update Sequence...........................30

Reference Input................................................31

N Counter.........................................................31

Prescaler and Prescaler Bias........................... 31

INT, FRAC, MOD, and R Counter

Relationship....................................................31

INT N Mode...................................................... 32

Phase Frequency Detector and Charge

Pump.............................................................. 32

Loop Filter........................................................ 32

Charge Pump Current Setup............................33

Bleed Current (CP_BLEED) Setup...................33

MUXOUT..........................................................34

Digital Lock Detect........................................... 34

VCO Autocalibration.........................................34

VCO Calibration Data Read Back.................... 34

VCO Calibration Data Manual Writing..............34

Autocalibration Lock Time................................ 34

Synthesizer Lock Timeout................................ 35

VCO Band Selection Time............................... 35

PLL Settling Time............................................. 35

Chip Temperature Read Back.......................... 35

RF Output Driver.............................................. 35

I/Q Mode Mixer Setup...................................... 36

I/Q Mode LO Nulling.........................................36

I/Q Mode Sideband Rejection Nulling ............. 36

IF Gain Control................................................. 36

IF Mode Mixer Setup........................................ 36

IF Mode LO Nulling.......................................... 37

IF Mode Sideband Rejection Nulling................ 37

Applications Information...................................... 38

IF AGC Configuration....................................... 38

Error Vector Magnitude Performance ..............38

PLL Lock Time in IF and I/Q Mode...................39

Power Up and Down........................................ 39

Outline Dimensions............................................. 64

Ordering Guide.................................................64

Evaluation Boards............................................ 64

REVISION HISTORY

5/2023—Rev. B to Rev. C

Change to Figure 29...................................................................................................................................... 15

Change to Figure 32 ..................................................................................................................................... 16

Deleted Figure 85; Renumbered Sequentially............................................................................................... 27

Changes to Prescaler and Prescaler Bias Section........................................................................................ 31

Changes to INT, FRAC, MOD, and R Counter Relationship Section.............................................................31

Changes to Table 9........................................................................................................................................40

Changes to Table 21......................................................................................................................................46

Changes to Table 38......................................................................................................................................51

Changes to Ordering Guide........................................................................................................................... 64

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