ADMV4530 datasheet(39/64 Pages) AD

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Data Sheet

ADMV4530

APPLICATIONS INFORMATION

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Rev. C | 39 of 64

PLL LOCK TIME IN IF AND I/Q MODE

Using the recommended autocalibration setup described in the

VCO Autocalibration section, the typical autocalibration lock time is

shown in Figure 98. These results reflect a VCO band selection

clock (fBSC) = 4 MHz.

Figure 98. LO Frequency vs. Time, REF_IN Frequency = 200 MHz, fBSC = 4

MHz

POWER UP AND DOWN

The ADMV4530 includes a power-down (PD) pin that when enabled

turns off the mixer and output driver section of the chip but keeps

the PLL and VCO active. For applications where a fast power-up

time is required, this standby mode is useful for muting the RF

output signal while keeping the PLL locked. Figure 99 shows the

typical response time of the PD pin.

Figure 99. Relative Output Level vs. Time, Power-Up and Power-Down

The chip can be set to its lowest power state by disabling the bias

for the PLL, VCO, and RF sections. To accomplish setting the chip

to its lowest power state, enable the following bits:

►

PLL_PD, Register 0x01E, Bit 2

►

VCO_PD, Register 0x027, Bit 2

►

RF_BIAS_PD, Register 0x100, Bit 7

When exiting the lowest power state and bringing the device

back to nominal operating conditions, the PLL must be relocked

by updating Register 0x010. Table 8 details the typical power

consumption for nominal, standby, and low power conditions.

Table 8. Typical Power Consumption at TA = 25°C

State

Power (W)

Test Conditions/Comments

Nominal

Maximum gain

I/Q Mode

1.8

IF Mode

2.5

Standby

PD pin high

I/Q Mode

0.7

IF Mode

1.4

Low Power

0.2

PD pin high, PLL, VCO, and RF disabled

ADMV4530 Datasheet(PDF) 39 Page - Analog Devices

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