ADMV4530 datasheet(52/64 Pages) AD

52 / 64 page

Data Sheet

ADMV4530

analog.com

Rev. C | 52 of 64

Table 38. Bit Descriptions for REG0027 (Continued)

Bits

Bit Name

Description

Reset

Recommended

Access

[1:0]

RF_PBS

Prescaler Bias Select.

0x0

0x1

R/W

00: +10%.

01: Nominal.

10: -10%.

11: -20%.

Address: 0x028, Reset: 0x00, Name: REG0028

Table 39. Bit Descriptions for REG0028

Bits

Bit Name

Description

Reset

Recommended

Access

[7:3]

RESERVED

Reserved.

0x0

R/W

[2:1]

LD_COUNT

Lock Detect Count. Sets the number of PFD cycles within the lock detect window before lock

detect goes high.

0x0

0x1

R/W

00: 1024 cycles.

01: 2048 cycles.

10: 4096 cycles.

11: 8192 cycles.

LOL_EN

Loss of Lock Enable. When loss of lock is enabled, if the digital lock detect is asserted, and the

reference signal is removed, then the digital lock detect goes low. It is recommended to set this

bit to 1.

0x0

0x1

R/W

0: disable.

1: enable.

Address: 0x02A, Reset: 0x00, Name: REG002A

Table 40. Bit Descriptions for REG002A

Bits

Bit Name

Description

Reset

Recommended

Access

[7:6]

RESERVED[1:0]

Reserved

0x0

R/W

CP_BLEED_POL

Bleed Polarity

0x0

R/W

0: negative (nominal)

1: positive (not recommended)

RESERVED

Reserved.

0x0

R/W

CSB_SYNC

CS Synchronization (with REF_IN Signal)

0x0

R/W

0: disable

1: enable

[2:0]

RESERVED

Reserved

0x0

R/W

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