ADMV4530 datasheet(32/64 Pages) AD

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Data Sheet

ADMV4530

THEORY OF OPERATION

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These calculations result in a low frequency resolution with no

residual frequency error. To apply the previous equation, perform

the following steps:

1. Calculate N by dividing fVCO/fPFD. The integer value of this

number forms INT.

2. Subtract INT from the full N value.

3. Multiply the remainder by 225. The integer value of this number

forms FRAC1.

4. Calculate MOD2 based on the channel spacing (fCHSP) by using

the following equation:

MOD2 = (fPFD/(GCD(fPFD, fCHSP)))

(8)

where:

fCHSP is the desired channel spacing frequency.

GCD(fPFD, fCHSP) is the greatest common divisor of the PFD

frequency and the channel spacing frequency.

5. Calculate FRAC2 by using the following equation:

FRAC2 = ((N − INT) × 225 – FRAC1) × MOD2

(9)

The FRAC2 and MOD2 fraction result in outputs with zero

frequency error for channel spacing when the following is true:

(fPFD/(GCD(fPFD, fCHSP)) = MOD2 < 16,383

(10)

If zero frequency error is not required, the MOD1 and MOD2

denominators operate together to create a 39-bit resolution

modulus.

INT N MODE

When FRAC1 and FRAC2 are equal to 0, the synthesizer operates

in Integer N mode. It is recommended to set the SD_PD bit

(Register 0x02B, Bit 0) to 1 to disable the Σ-Δ modulators (SDMs),

which improves the in band phase noise and reduces any additional

Σ-Δ noise.

PHASE FREQUENCY DETECTOR AND

CHARGE PUMP

The phase frequency detector takes inputs from the R counter

and N counter to produce an output that is proportional to the

phase and frequency differences between these counters. This

proportional information is then output to a charge pump circuit that

generates current to drive an external loop filter that is then used to

appropriately increase or decrease the VTUNE tuning voltage.

Figure 91 shows a simplified schematic of the phase frequency

detector and charge pump. Note that the phase frequency detector

includes a fixed delay element that is used to ensure that there is

no dead zone in the phase frequency detector transfer function for

consistent reference spur levels.

Figure 91. Phase Frequency Detector and Charge Pump Simplified

Schematic

LOOP FILTER

Defining a loop filter for a PLL is dependent on several dynamics,

such as the fPFD, the N counter value, the KVCO, and the selected

charge pump current (ICP). A higher fPFD has the advantage of low-

ering in band phase noise performance at the expense of integer

boundary spur levels when operating in fractional-N mode. Conse-

quently, a lower fPFD can allow the PLL to operate in integer N

mode, which can eliminate integer boundary spurs at the expense

of higher in band phase noise performance. Given the trade-offs,

care must be taken with frequency planning and fPFD selection to

ensure the appropriate in band phase noise performance is met

with acceptable spur levels for the end application.

The loop filter, as implemented using one of the ADMV4530 eval-

uation boards (see the Ordering Guide section), is a third-order

passive filter, as shown in Figure 92. The filter is designed with the

following simulation input parameters: fPFD = 100 MHz, KVCO = 155

MHz/V, fVCO = 15 GHz, and ICP = 4.2 mA. The resulting loop filter

bandwidth and phase margin are 540 kHz and 55°, respectively, for

the following component values: C1 = 150 pF, C2 = 15 nF, C3 =

20 pF, C4 = do not install (DNI), R1 = 910 Ω, R2 = 910 Ω, and R3

= 0 Ω. For additional guidance with loop filter simulations on the

ADMV4530, contact Analog Devices for Technical Support.

Figure 92. Recommended Loop Filter

ADMV4530 Datasheet(PDF) 32 Page - Analog Devices

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