PSD913F2 datasheet(51/94 Pages) STMICROELECTRONICS

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Preliminary Information

PSD9XX Family

The

PSD9XX

Functional

Blocks

(cont.)

9.4.3.1 Control Register

Any bit set to ‘0’ in the Control Register sets the corresponding Port pin to MCU I/O Mode,

and a ‘1’ sets it to Address Out Mode. The default mode is MCU I/O. Only Ports A and B

have an associated Control Register.

9.4.3.2 Direction Register

The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to

‘1’ in the Direction Register will cause the corresponding pin to be an output, and any bit

set to ‘0’ will cause it to be an input. The default mode for all port pins is input.

Figures 20 and 22 show the Port Architecture diagrams for Ports A, B and C, respectively.

The direction of data flow for Ports A, B, and C are controlled by the direction register.

An example of a configuration for a port with the three least significant bits set to output

and the remainder set to input is shown in Table 26. Since Port D only contains three pins,

the Direction Register for Port D has only the three least significant bits active.

Direction Register Bit

Port Pin Mode

Input

Output

Table 24. Port Pin Direction Control

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

000

Table 26. Port Direction Assignment Example

9.4.3 Port Configuration Registers (PCRs)

Each port has a set of PCRs used for configuration. The contents of the registers can be

accessed by the microcontroller through normal read/write bus cycles at the addresses

given in Table 7. The addresses in Table 7 are the offsets in hex from the base of the

CSIOP register.

The pins of a port are individually configurable and each bit in the register controls its

respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs,

shown in Table 23, are used for setting the port configurations. The default power-up state

for each register in Table 23 is 00h.

Port

MCU Access

Control

A,B

Write/Read

Direction

A,B,C,D

Write/Read

Drive Select*

A,B,C,D

Write/Read

Table 23. Port Configuration Registers

*NOTE: See Table 27 for Drive Register bit definition.

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