M25P05-AVMP6TP datasheet(19/52 Pages) NUMONYX

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M25P05-A

Instructions

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6.1

Write enable (WREN)

The write enable (WREN) instruction (Figure 7) sets the write enable latch (WEL) bit.

The write enable latch (WEL) bit must be set prior to every page program (PP), sector erase

(SE), bulk erase (BE) and write status register (WRSR) instruction.

The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the

instruction code, and then driving Chip Select (S) High.

Figure 7.

Write enable (WREN) instruction sequence

Table 4.

Instruction set

Instruction

Description

One-byte instruction

code

Address

bytes

Dummy

bytes

Data

bytes

WREN

Write enable

0000 0110

06h

WRDI

Write disable

0000 0100

04h

RDID(1)

The read identification (RDID) instruction is available only in products with process technology code X and

Y (see application note AN1995).

Read identification

1001 1111

9Fh

1 to 3

RDSR

Read status register

0000 0101

05h

1 to

∞

WRSR

Write status register

0000 0001

01h

READ

Read data bytes

0000 0011

03h

1 to

∞

FAST_READ

Read data bytes at higher

speed

0000 1011

0Bh

1 to

∞

Page program

0000 0010

02h

1 to 256

Sector erase

1101 1000

D8h

Bulk erase

1100 0111

C7h

Deep power-down

1011 1001

B9h

RES

Release from deep power-

down, and read electronic

signature

1010 1011

ABh

1 to

∞

Release from deep power-

down

AI02281E

34567

High Impedance

Instruction

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