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M25P05-AVMP6TP Datasheet(PDF) 42 Page - Numonyx B.V

No. de pieza M25P05-AVMP6TP
Descripción Electrónicos  512 Kbit, serial Flash memory, 50 MHz SPI bus interface
PDF  52 Pages
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Fabricante Electrónico  NUMONYX [Numonyx B.V]
Página de inicio  http://www.numonyx.com
Logo NUMONYX - Numonyx B.V

M25P05-AVMP6TP Datasheet(HTML) 42 Page - Numonyx B.V

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DC and AC parameters
M25P05-A
42/52
Table 17.
AC characteristics (50 MHz operation)
50 MHz available only in products with process technology code Y(1)(2)
Test conditions specified in Table 10 and Table 11.
Symbol
Alt.
Parameter
Min
Typ
Max
Unit
fC
fC
Clock frequency(1) for the following instructions: FAST_READ,
PP, SE, BE, DP, RES, WREN, WRDI, RDID, RDSR, WRSR
D.C.
50
MHz
fR
Clock frequency for read instructions
D.C.
25
MHz
tCH
(3)
tCLH Clock high time
9
ns
tCL
(3)
tCLL Clock low time
9
ns
tCLCH
(4)
Clock rise time(5) (peak to peak)
0.1
V/ns
tCHCL
(4)
Clock fall time(5) (peak to peak)
0.1
V/ns
tSLCH
tCSS S active setup time (relative to C)
5
ns
tCHSL
S not active hold time (relative to C)
5
ns
tDVCH
tDSU Data in setup time
2
ns
tCHDX
tDH
Data in hold time
5
ns
tCHSH
S active hold time (relative to C)
5
ns
tSHCH
S not active setup time (relative to C)
5
ns
tSHSL
tCSH S deselect time
100
ns
tSHQZ
(4)
tDIS
Output disable time
8
ns
tCLQV
tV
Clock Low to Output Valid
8
ns
tCLQX
tHO
Output hold time
0
ns
tHLCH
HOLD setup time (relative to C)
5
ns
tCHHH
HOLD hold time (relative to C)
5
ns
tHHCH
HOLD setup time (relative to C)
5
ns
tCHHL
HOLD hold time (relative to C)
5
ns
tHHQX
(4)
tLZ
HOLD to Output Low-Z
8
ns
tHLQZ
(4)
tHZ
HOLD to Output High-Z
8
ns
tWHSL
(6)
Write protect setup time
20
ns
tSHWL
(6)
Write protect hold time
100
ns
tDP
(4)
S High to deep power-down mode
3
µs
tRES1
(4)
S High to standby mode without electronic signature read
30
µs
tRES2
(4)
S High to standby mode with electronic signature read
30
µs
1.
Details of how to find the process on the device marking are given in application note AN1995.
2.
50 MHz operation is also available in products with process technology code X, but with a reduced supply voltage range
(2.7 to 3.6 V).
3.
tCH + tCL must be greater than or equal to 1/ fC.
4.
Value guaranteed by characterization, not 100% tested in production.
5.
Expressed as a slew-rate.
6.
Only applicable as a constraint for a WRSR instruction when SRWD is set to ‘1’.



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