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IS25LE01G-RILA3 Datasheet(PDF) 155 Page - Integrated Silicon Solution, Inc |
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IS25LE01G-RILA3 Datasheet(HTML) 155 Page - Integrated Silicon Solution, Inc |
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155 / 186 page  IS25LE01G IS25WE01G Integrated Silicon Solution, Inc.- www.issi.com 155 Rev. A6 01/14/2025 8.54 ERASE PPB OPERATION (ERPPB, E4h) The Erase PPB (ERPPB) command sets all PPB bits to “1”. Before the ERPPB command can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device, which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations. The instruction code is shifted in by the rising edges of the SCK signal. CE# must be driven high after the eighth bit of the instruction byte has been latched in. This will initiate the beginning of internal erase cycle, which involves the pre-programming and erase of the entire PPB memory array. Without CE# being driven high after the eighth bit of the instruction, the PPB erase operation will not be executed. With the internal erase cycle in progress, the user can read the value of the Write In Progress (WIP) bit to check if the operation has been completed. The WIP bit will indicate “1” when the erase cycle is in progress and “0” when the erase cycle has been completed. When the ERPPB operation is completed, the WEL is set to “0”. Erase suspend is not allowed during PPB Erase. Figure 8.122 Erase PPB Sequence In SPI Mode Instruction = E4h CE# SCK SI 0 1 2 3 4 5 6 7 Mode 3 Mode 0 SO High Impedance Figure 8.123 Erase PPB Sequence In QPI Mode E4h CE# SCK IO[3:0] 0 1 Mode 3 Mode 0 |
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