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IS25LE01G-RILA3 Datasheet(PDF) 95 Page - Integrated Silicon Solution, Inc

No. de pieza IS25LE01G-RILA3
Descripción Electrónicos  SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  186 Pages
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Fabricante Electrónico  ISSI [Integrated Silicon Solution, Inc]
Página de inicio  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LE01G-RILA3 Datasheet(HTML) 95 Page - Integrated Silicon Solution, Inc

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IS25LE01G
IS25WE01G
Integrated Silicon Solution, Inc.- www.issi.com
95
Rev. A6
01/14/2025
8.16 WRITE ENABLE OPERATION (WREN, 06h)
The Write Enable (WREN) instruction is used to set the Write Enable Latch (WEL) bit. The WEL bit is reset to the
write-protected state after power-up. The WEL bit must be write enabled before any write operation, including
Sector Erase, Block Erase, Chip Erase, Page Program, Program Information Row, Write Status Register, Write
Function Register, Set Non-Volatile Read Register, Set Non-Volatile Extended Read Register operations, Set
Volatile Read Register and Set Volatile Extended Read Register. The WEL bit will be reset to the write-protected
state automatically upon completion of a write operation. The WREN instruction is required before any above
operation is executed.
Figure 8.41 Write Enable Sequence In SPI Mode
Instruction = 06h
CE#
SCK
SI
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SO
High Impedance
Figure 8.42 Write Enable Sequence In QPI Mode
06h
CE#
SCK
IO[3:0]
0
1
Mode 3
Mode 0



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