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IS25LE01G-RILA3 Datasheet(PDF) 78 Page - Integrated Silicon Solution, Inc

No. de pieza IS25LE01G-RILA3
Descripción Electrónicos  SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  186 Pages
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Fabricante Electrónico  ISSI [Integrated Silicon Solution, Inc]
Página de inicio  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LE01G-RILA3 Datasheet(HTML) 78 Page - Integrated Silicon Solution, Inc

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IS25LE01G
IS25WE01G
Integrated Silicon Solution, Inc.- www.issi.com
78
Rev. A6
01/14/2025
Figure 8.15 Fast Read Quad I/O Sequence (EBh [EXTADD=0], 3-byte address)
CE #
SCK
5
1
Data Out 1
Instruction = EBh
20
CE #
SCK
4
0
4
0
3-byte Address
High Impedance
16
12
8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Mode 3
Mode 0
...
tV
IO0
IO1
4
0
5
1
5
1
4
0
4
0
5
1
4
0
IO0
IO1
21
5
1
5
1
17
13
9
22
6
2
6
2
18
14
10
23
7
3
7
3
19
15
11
Mode Bits
IO2
IO3
6
2
6
2
6
2
6
2
7
3
7
3
7
3
7
3
Data Out 2 Data Out 3 Data Out 4
IO2
IO3
1
0
5
1
...
4
0
...
2
6
2
...
3
7
3
...
5
4
6
7
6 Dummy Cycles
Data Out 5 Data Out 6
Notes:
1.
If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.



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