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IS25LE01G-RILA3 Datasheet(PDF) 69 Page - Integrated Silicon Solution, Inc

No. de pieza IS25LE01G-RILA3
Descripción Electrónicos  SERIAL FLASH MEMORY 133/104MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC
PDF  186 Pages
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Fabricante Electrónico  ISSI [Integrated Silicon Solution, Inc]
Página de inicio  http://www.issi.com
Logo ISSI - Integrated Silicon Solution, Inc

IS25LE01G-RILA3 Datasheet(HTML) 69 Page - Integrated Silicon Solution, Inc

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IS25LE01G
IS25WE01G
Integrated Silicon Solution, Inc.- www.issi.com
69
Rev. A6
01/14/2025
Figure 8.8 Fast Read Dual I/O Sequence (BBh [EXTADD=1] or BCh, 4-byte address)
4-byte Address
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
36
41
...
Instruction = BBh/BCh
7
5
3
7
5
1
3
1
Data Out 1
30
CE #
SCK
2
0
6
4
High Impedance
28
26
...
0
1
2
3
4
5
6
7
8
9
10
...
Mode 3
Mode 0
tV
31
3
1
7
5
29
27
...
IO0
IO1
3
1
2
0
6
4
2
6
4
0
2
0
4 Dummy Cycles
7
5
3
1
6
4
2
0
7
5
...
6
4
...
CE #
SCK
IO0
IO1
Data Out 2
Data Out 3
Mode Bits
Mode Bits
Notes:
1.
If the mode bits=AXh (where X is don’t care), it can execute the AX read mode (without command). When the mode
bits are different from AXh, the device exits the AX read operation.
2. Number of dummy cycles depends on clock speed. Detailed information in Table 6.11 Read Dummy Cycles.
3. Sufficient dummy cycles are required to avoid I/O contention. If the number of dummy cycles and AX bits cycles
are same, then X should be Hi-Z.



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