TMP112DX datasheet(31/46 Pages) TI1

31 / 46 page

Not to scale

0.01µF

2C Bus

Via to Power Plane

Via to Internal Plane

Internal Layer Trace

Top/Bottom Layer Trace

Via to Ground Plane

Center Pin Layout (Address Variant)

Figure 8-6. ADD0 Pin Layout Example (X2SON-5 package)

When using the ALERT pin of the device, a 4 mil trace can be routed between pins 1 and 5 or pins 2 and 4.

This signal can be either routed out in between the pads or on a different layer using a via within the center pad

as shown in Figure 8-7. Both of these methods have constraints that must be considered as explained below.

Ultimately, choosing one of these methods depends on the specifications of the board manufacturing process:

• Option 1 (Routing in between pads): introduces trace clearance and trace width limitations. As the

maximum space between pads is 0.26 mm (10.2 mil), assuming a trace width of 0.1 mm (4 mil) limits the

minimum clearance to 0.08 mm (3.15 mil).

• Option 2 (Routing on a different layer using a via): has specific benefits to the user application. For

instance, minimum trace clearance and trace width are higher but require a via on the center pad with

specific dimensions. The via diameter must be less than 0.305 mm (13.78 mil) to keep the via smaller than

the center pad and a minimum drill diameter of 0.1 mm (4 mil) can be assumed to avoid manufacturing

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TMP112, TMP112D

SBOS473L – MARCH 2009 – REVISED JULY 2024

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TMP112DX Datasheet(PDF) 31 Page - Texas Instruments