ICSSSTUAF32868B

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

COMMERCIAL TEMPERATURE GRADE

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

16

ICSSSTUAF32868B

7102/2

Register Timing

NOTE:

1.If the data is clocked in on the n clock pulse, the QERR output signal will be generated on the n+2 clock pulse, and

it will be valid on the n+3 clock pulse. If an error occurs and the QERR output is driven LOW, it stays latched LOW

for a minimum of two clock cycles or until RESET is driven LOW.