ICSSSTUAF32868B

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

COMMERCIAL TEMPERATURE GRADE

28-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2

14

ICSSSTUAF32868B

7102/2

Timing Requirements Over Recommended Operating Free-Air Temperature

Range

Switching Characteristics Over Recommended Free Air Operating Range

(unless otherwise noted)

Symbol

Parameter

VDD = 1.8V ± 0.1V

Units

Min.

Max.

fCLOCK

Clock Frequency

410

MHz

tW

Pulse Duration, CLK, CLK HIGH or LOW

1

ns

tACT1,2

1

This parameter is not production tested.

2

VREF must be held at a valid input voltage level and data inputs must be held at valid voltage levels for

a minimum time of tACT (max) after RESET is taken HIGH.

Differential Inputs Active Time

10

ns

tINACT1,3

3

VREF data and clock inputs must be held at valid input voltage levels (not floating) for a minimum time

of tINACT (max) after RESET is taken LOW.

Differential Inputs Inactive Time

15

ns

tSU

Setup

Time

DCS0 before CLK

↑, CLK↓, DCS1 and CSGEN HIGH;

DCS1 before CLK

↑, CLK↓, DCS0 and CSGEN HIGH;

0.7

ns

DCS0 before CLK

↑, CLK↓, DCS1 LOW and CSGEN

HIGH or LOW; DCS1 before CLK

↑, CLK↓, DCS0

LOW and CSGEN HIGH or LOW

0.5

ns

DODTn, DCKEn, PAR_IN, and data before CLK

↑,

CLK

↓

0.5

ns

tH

Hold

Time

DCSn, DODT,n DCKEn, and data after CLK

↑, CLK↓

0.5

ns

PAR_IN after CLK

↑, CLK↓

0.5

ns

Symbol

Parameter

VDD = 1.8V ± 0.1V

Units

Min.

Max.

fMAX

Max Input Clock Frequency

410

MHz

tPDM

Propagation Delay, single bit switching, CLK

↑ / CLK↓ to Qn

1.3

1.9

ns

tPDMSS

Propagation Delay, simultaneous switching, CLK

↑ / CLK↓ to Qn

2

ns

tLH

LOW to HIGH Propagation Delay, CLK

↑ / CLK↓ to QERR

0.9

3

ns

tHL

HIGH to LOW Propagation Delay, CLK

↑ / CLK↓ to QERR

0.7

2.4

ns

tPLH

HIGH to LOW Propagation Delay, RESET

↓ to Qn↓

3ns

tPHL

LOW to HIGH Propagation Delay, RESET

↓ to QERR↑

3ns