ADP5056ACCZ-R7 datasheet(17/31 Pages) AD

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Data Sheet

ADP5056

Rev. 0 | Page 17 of 31

In the configuration shown in Figure 35, the phase shift between

Channel 1 of the first ADP5056 device and Channel 1 of the

second ADP5056 device is 0° (see Figure 36).

CH1 2.0V/DIV 1

MΩ BW: 500M

CH2 5.0V/DIV 1

MΩ BW: 20.0M

CH3 5.0V/DIV 1

MΩ BW: 20.0M

500ns/DIV 200MS/s

A CH1

2.88V

5.0ns/pt

Figure 36. Waveforms of Two ADP5056 Devices Operating in

Synchronization Mode, Channel 1 = Synchronization Clock Output of First

ADP5056 Device, Channel 2 = SW1 of First ADP5056 Device, Channel 3 =

SW1 of Second ADP5056 Device

SOFT START

The buck regulators in the ADP5056 include soft start circuitry

that ramps the output voltage in a controlled manner during

startup, thereby limiting the inrush current. The soft start time

for all channels is fixed at 0.83 × tSET timer (2.2 ms or 17.3 ms,

depending on RCFG2 value).

FUNCTION CONFIGURATIONS (CFG1 AND CFG2)

The ADP5056 includes the CFG1 pin and CFG2 pin to decode the

function configurations for all channels. The logic statuses of

each pin is decoded by connecting one resistor to ground. It is

recommended to use ±1% resistor tolerance to achieve accurate

decoding.

This decoder circuitry only works in the initiation stage of the

ADP5056 when VBIAS passes the power-on reset (POR)

threshold. Therefore, those configurations are latched into

internal registers and cannot be changed in operation.

The CFG1 pin can be used to program the SYNC/MODE pin or

CLKOUT, the load output capability, and parallel operation for

all channels. Table 6 provides the values of RCFG1 needed to set

different functionality in the CFG1 pin.

The CFG2 pin can be used to program the tSET timer (2.6 ms or

20.8 ms), fast transient functionality, and sequence for the three

channels. Table 7 provides the values of RCFG2 needed to set

different functionality in the CFG2 pin.

Table 6. Configuration by the CFG1 Pin

RCFG1

(kΩ),

±1%

GPIO

Output Capability

Channel 1

Channel 2

Channel 3

0 (GND)

SYNC/MODE

7 A

3 A

14.3

SYNC/MODE

7 A

1.5 A

16.9

SYNC/MODE

7 A

3.5 A

3 A

20.0

SYNC/MODE

7 A

3.5 A

1.5 A

23.7

SYNC/MODE

Interleaved

parallel (14 A)

Interleaved

parallel (14 A)

3 A

Open

SYNC/MODE

3.5 A

1.5 A

32.4

SYNC/MODE

In phase

parallel (14 A)

In phase

parallel (14 A)

3 A

39.2

Clock output

7 A

3 A

47.5

Clock output

7 A

1.5 A

57.6

Clock output

7 A

3.5 A

3 A

71.5

Clock output

7 A

3.5 A

1.5 A

90.9

Clock output

3.5 A

7 A

3 A

127

Clock output

Interleaved

parallel (14 A)

Interleaved

parallel (14 A)

3 A

200

Clock output

3.5 A

1.5 A

511

Clock output

In phase

parallel (14 A)

In phase

parallel (14 A)

3 A

Table 7. Configuration by the CFG2 Pin

RCFG2 (kΩ),

±1%

tSET timer

(ms)

Fast

Transient

Start-Up Sequence

0 (GND)

2.6

Disable

No delay

14.3

2.6

Disable

Channel 1, Channel 2,

Channel 3

16.9

2.6

Disable

Channel 2, Channel 1,

Channel 3

2.6

Disable

Channel 3, Channel 1,

Channel 2

23.7

2.6

Enable

No delay

32.4

2.6

Enable

Channel 1, Channel 2,

Channel 3

39.2

2.6

Enable

Channel 3, Channel 1,

Channel 2

Open

20.8

Disable

No delay

47.5

20.8

Disable

Channel 1, Channel 2,

Channel 3

57.6

20.8

Disable

Channel 2, Channel 1,

Channel 3

71.5

20.8

Disable

Channel 3, Channel 1,

Channel 2

90.9

20.8

Enable

No delay

127

20.8

Enable

Channel 1, Channel 2,

Channel 3

200

20.8

Enable

Channel 2, Channel 1,

Channel 3

511

20.8

Enable

Channel 3, Channel 1,

Channel 2

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