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ADP5056

Data Sheet

Rev. 0 | Page 16 of 31

OSCILLATOR

By connecting a resistor from the RT pin to ground, the fSW of the

ADP5056 can be set to a value between 250 kHz and 2500 kHz.

Calculate the RT resistor value in kΩ as follows:

0.998

167,305

Figure 32 shows the typical relationship between the fSW and the RT

resistor. The adjustable frequency allows users to make decisions

based on the trade-off between efficiency and solution size.

3000

2500

2000

1000

1500

500

130

230

330

430

530

630

730

RT RESISTANCE (kΩ)

Figure 32. Switching Frequency vs. RT Resistance

Out-Of-Phase Operation

By default, the phase shift between Channel 1, Channel 2, and

Channel 3 is 120°. This value provides the benefits of out-of-

phase operation by reducing the input ripple current and

lowering the ground noise.

CH2

CH1

CH3

120° PHASE SHIFT

0° REFERENCE

240° PHASE SHIFT

Figure 33. Phase Shift Diagram, Three Buck Regulators

In the in phase parallel operation configuration of Channel 1

and Channel 2, both channels operate in the same phase of

Channel 1.

In the interleaved parallel operation configuration of Channel 1

and Channel 2, the phase shift between Channel 1, Channel 2, and

Channel 3 is 0°, 180°, and 240°.

CH1 5.0V/DIV 1

MΩ BW: 500M

CH2 5.0V/DIV 1

MΩ BW: 20.0M

CH3 5.0V/DIV 1

MΩ BW: 20.0M

2.0µs/DIV 100MS/s

A CH1

500mV

10.0ns/pt

Figure 34. 120° Phase Shift Waveforms, Three Buck Regulators:

Channel 1 = SW1, Channel 2 = SW2, Channel 3 = SW3

SYNCHRONIZATION INPUT/OUTPUT

The switching frequency of the ADP5056 can be synchronized

to an external clock with a frequency range from 250 kHz to

2700 kHz. The ADP5056 automatically detects the presence of

an external clock applied to the SYNC/MODE pin, and the

switching frequency transitions smoothly to the frequency of

the external clock. When the external clock signal stops, the

device automatically switches back to the internal clock and

continues to operate.

Note that the internal switching frequency set by the RT pin must

be programmed to a value that is close to the external clock value

for successful synchronization. The suggested frequency difference

is less than ±15% in typical applications.

The SYNC/MODE pin can be configured as a synchronization

clock output by the CFG1 pin (refer to Table 6). A positive clock

pulse with a 50% duty cycle and VREG voltage level is generated

at the SYNC/MODE pin with a frequency equal to the internal

switching frequency set by the RT pin.

Figure 35 shows two ADP5056 devices configured for frequency

synchronization mode. One ADP5056 device is configured as the

clock output to synchronize another ADP5056 device.

SYNC/

MODE

SYNC/

MODE

ADP5056

(1)

CFG1

(CLOCK MASTER)

(SLAVE)

ADP5056

(2)

(CLOCK OUT) (SYNC IN)

CFG1

Figure 35. Two ADP5056 Devices Configured for Synchronization Mode

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