LP8733 datasheet(30/86 Pages) TI

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LP8733

SNVSBK2 – SEPTEMBER 2019

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The regulator output voltage monitoring (not current limit monitoring) can be selected for the PGOOD indication.

This selection is individual for both buck regulators (only master buck in dual-phase configuration) and LDO

regulators, and is set by the EN_PGOOD_BUCKx bits in the PGOOD_CTRL_1 register and the

EN_PGOOD_LDOx bits in the PGOOD_CTRL_1 register. When a regulator is disabled, the monitoring is

automatically masked to prevent it forcing the PGOOD inactive. A thermal warning can also be selected for the

PGOOD indication with the EN_PGOOD_TWARN bit in the PGOOD_CTRL_2 register. The monitoring from all

the output rails, thermal warning (TDIE_WARN_STAT), input overvoltage interrupt (OVP_INT), and thermal

shutdown interrupt (TDIE_SD_INT) are combined, and the PGOOD pin is active only if all the selected sources

shows a valid status.

The type of output voltage monitoring for the PGOOD signal is selected by the PGOOD_WINDOW_x bits in the

PGOOD_CTRL_1 register. If the bit is 0, only undervoltage is monitored; if the bit is 1, both undervoltage and

overvoltage are monitored.

The polarity and the output type (push-pull or open-drain) are selected by the PGOOD_POL and PGOOD_OD

bits in the PGOOD_CTRL_1 register.

The PGOOD is only active and asserted when all enabled power resource output voltages are within specified

tolerance for each requested and programmed output voltage.

The PGOOD is inactive and de-asserted if any enabled power resource output voltages is outside specified

tolerance for each requested and programmed output voltage.

The device OTP setting selects either gated (or unusual) or continuous (or invalid) mode of operation.

7.3.8.1.1

PGOOD Pin Gated Mode

The gated (or unusual) mode of operation is selected by setting the PGOOD_MODE bit to 0 in the

PGOOD_CTRL_2 register.

For the gated mode of operation, the PGOOD behaves as follows:

•

PGOOD is set to active or asserted state upon exiting the OTP configuration as an initial default state.

•

PGOOD status is suspended or unchanged during an 800-µs gated time period, thereby gating-off the status

indication.

•

During normal power-up sequencing and requested voltage changes, the PGOOD state is not changed during

an 800-µs gated time period. It typically remains active or asserted for normal conditions.

•

During an abnormal power-up sequencing and requested voltage changes, the PGOOD status could change

to inactive or de-asserted after an 800-µs gated time period if any output voltage is outside of regulation

range.

•

Using the gated mode of operation could allow the PGOOD signal to initiate an immediate power shutdown

sequence if the PGOOD signal is wired-OR with signal connected to the EN input. This type of circuit

configuration provides a smart PORz function for processor that eliminates the need for additional

components to generate PORz upon start-up and to monitor voltage levels of key voltage domains.

Each detected fault sets the correcting fault bit in the PG_FAULT register to 1. The detected fault must be

cleared to continue the PGOOD monitoring. The overvoltage and thermal shutdown are cleared by writing 1 to

the OVP_INT and TDIE_SD_INT interrupt bits in the INT_TOP_1 register. The regulator fault is cleared by writing

1 to the corresponding register bit in the PG_FAULT register. The interrupts can also be cleared with the VANA

UVLO by toggling the input supply. An example of the PGOOD pin operation in gated mode is shown in

Figure 17.

LP8733 Datasheet(PDF) 30 Page - Texas Instruments

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