LP8733 datasheet(37/86 Pages) TI

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LP8733

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SNVSBK2 – SEPTEMBER 2019

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No glitch filtering, only synchronization.

The GPO pins are configured with the following bits:

•

The GPOx_OD bit in The GPO_CTRL register defines the type of the output, either push-pull with V(VANA)

level or open drain.

The logic level of the GPOx pin is set by the EN_GPOx bit in the GPO_CTRL register.

The control of the GPOs can be included to start-up and shutdown sequences. The GPO control for a sequence

with an EN pin is selected by the GPOx_EN_PIN_CTRL bit in the GPO_CTRL register. For start-up and

shutdown sequence control, see Enable and Disable Sequences.

7.3.10 Digital Signal Filtering

The digital signals have a debounce filtering. The signal or supply is sampled with a clock signal and a counter.

This results as an accuracy of one clock period for the debounce window.

Table 5. Digital Signal Filtering

EVENT

SIGNAL/SUPPLY

RISING EDGE

FALLING EDGE

LENGTH

Enable/disable for BUCKx,

LDOx or GPOx

3 µs(1)

VANA UVLO

VANA

3 µs(1) (VANA voltage rising)

Immediate (VANA voltage falling)

VANA overvoltage

VANA

1 µs (VANA voltage rising)

20 µs (VANA voltage falling)

Thermal warning

TDIE_WARN_INT

20 µs

Thermal shutdown

TDIE_SD_INT

20 µs

Current limit

VOUTx_ILIM

20 µs

Overload

FB_B0, FB_B1,

VOUT_LDO0, VOUT_LDO1

1 ms

N/V

PGOOD pin and power-good

interrupt

PGOOD / FB_B0, FB_B1,

VOUT_LDO0, VOUT_LDO1

6 µs

LP8733 Datasheet(PDF) 37 Page - Texas Instruments

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