LP8733 datasheet(6/86 Pages) TI

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LP8733

SNVSBK2 – SEPTEMBER 2019

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(1)

For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

note.

6.4 Thermal Information

THERMAL METRIC(1)

LP8733xx

UNIT

RHD (VQFN)

28 PINS

RθJA

Junction-to-ambient thermal resistance

36.7

°C/W

RθJCtop

Junction-to-case (top) thermal resistance

26.6

°C/W

RθJB

Junction-to-board thermal resistance

8.9

°C/W

ψJT

Junction-to-top characterization parameter

0.4

°C/W

ψJB

Junction-to-board characterization parameter

8.8

°C/W

RθJCbot

Junction-to-case (bottom) thermal resistance

2.2

°C/W

(1)

All voltage values are with respect to network ground.

(2)

Minimum (MIN) and Maximum (MAX) limits are specified by design, test, or statistical analysis. Typical (TYP) numbers are not verified,

but do represent the most likely norm.

(3)

The maximum output current can be limited by the forward current limit ILIM FWD. The power dissipation inside the die increases the

junction temperature and limits the maximum current depending of the length of the current pulse, efficiency, board and ambient

temperature.

6.5 Electrical Characteristics

Limits apply over the junction temperature range –40°C

≤ TJ ≤ +140°C, specified VVANA, VVIN_Bx, VVIN_LDOx, VVOUT_Bx, VVOUT_LDOx

and IOUT range, unless otherwise noted. Typical values are at TJ = 25°C, VVANA = VVIN_Bx = VVIN_LDOx = 3.7 V, and VOUT = 1 V,

unless otherwise noted.

(1) (2).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

EXTERNAL COMPONENTS

CIN_BUCK

Input filtering

capacitance for buck

regulators

Effective capacitance, connected from VIN_Bx

to PGND_Bx

1.9

µF

COUT_BUCK

Output filtering

capacitance for buck

regulators

Effective capacitance per phase

500

µF

CPOL_BUCK

Point-of-load (POL)

capacitance for buck

regulators

Optional POL capacitance

µF

COUT-

TOTAL_BUCK

Buck output capacitance,

total (local and POL)

Total output capacitance per phase

500

µF

CIN_LDO

Input filtering

capacitance for LDO

regulators

Effective capacitance, connected from

VIN_LDOx to AGND. CIN_LDO must be at least

two times larger than COUT_LDO

0.6

2.2

µF

COUT_LDO

Output filtering

capacitance for LDO

regulators

Effective capacitance

0.4

2.7

µF

ESRC

Input and output

capacitor ESR

[1-10] MHz

mΩ

Inductor

Inductance of the inductor

0.47

µH

–30%

30%

DCRL

Inductor DCR

mΩ

BUCK REGULATORS

V(VIN_Bx),

V(VANA)

Input voltage range

VIN_Bx and VANA pins must be connected to

the same supply line

2.8

3.7

5.5

VOUT_Bx

Output voltage

Programmable voltage range

0.7

3.36

Step size, 0.7 V

≤ VOUT < 0.73 V

Step size, 0.73 V

≤ VOUT < 1.4 V

Step size, 1.4 V

≤ VOUT ≤ 3.36 V

IOUT_Bx

Output current

Output current, single-phase output

3(3)

Output current, dual-phase output

6(3)

LP8733 Datasheet(PDF) 6 Page - Texas Instruments

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