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LP8733 Datasheet(PDF) 18 Page - Texas Instruments |
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LP8733 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 86 page  FB + - + - POWER GOOD LOOP COMP RAMP GENERATOR HS FET CURRENT SENSE LS FET CURRENT SENSE GATE CONTROL IADC VDAC ERROR AMP GND NEG CURRENT LIMIT ZERO CROSS DETECT SW POS CURRENT LIMIT VIN VOUT CONTROL BLOCK PROGRAMMABLE PARAMETERS SLAVE INTERFACE VOLTAGE SETTING SLEW RATE CONTROL MASTER INTERFACE Copyright © 2016, Texas Instruments Incorporated 18 LP8733 SNVSBK2 – SEPTEMBER 2019 www.ti.com Product Folder Links: LP8733 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated Feature Description (continued) • Power Good flag with maskable interrupt • Power Good signal (PGOOD) with selectable sources • Average output current sensing (for PFM entry, phase shedding and adding in dual-phase configuration, and load current measurement) • Current balancing between the phases of the converter in dual-phase configuration • Differential voltage sensing from point of the load in dual-phase configuration • Dynamic phase shedding and adding, each output being phase shifted in dual-phase configuration The following parameters can be programmed via registers, the default values are set by OTP bits: • Output voltage • Forced PWM operation • Forced dual-phase operation (forces also the PWM operation) • Switch current limit • Output voltage slew rate • Enable and disable delays There are two modes of operation for the buck converter, depending on the output current required: pulse-width modulation (PWM) and pulse-frequency modulation (PFM). The converter operates in PWM mode at high load currents of approximately 600 mA or higher. When operating in PWM mode in dual-phase configuration the phases are automatically added and shedded based on the load current level. Lighter output current loads cause the converter to automatically switch into PFM mode for reduced current consumption when forced PWM mode is disabled. The forced PWM mode can be selected to maintain fixed switching frequency at all load current levels. A block diagram of a single core is shown in Figure 8. Figure 8. Detailed Block Diagram Showing One Core 7.3.1.2 Dual-Phase Operation and Phase-Adding/Shedding Under heavy load conditions, the dual-phase converter switches both channel 180° apart. As a result, the dual- phase converter has an effective ripple frequency two times greater than the switching frequency of a single phase. However, the parallel operation decreases the efficiency at light load conditions. In order to overcome this operational inefficiency, the LP8733xx can change the number of active phases to optimize efficiency for the variations of the load. This is called phase adding and shedding. The concept is shown in Figure 9. The converter can be forced to dual-phase operation by the BUCK0_FPWM_MP bit in the BUCK0_CTRL_1 register. If the regulator operates in forced dual-phase mode the forced PWM operation is automatically used. If the dual-phase operation is not forced, the number of phases are added and shedded automatically to follow the required output current. |
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