CS4210 datasheet(83/102 Pages) NSC

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4.4.25.3 Async Response Receive Context Control

The ContextControl Set/Clear registers contain bits that

control options, operational state, and status for the DMA

context. Software can set selected bits by writing ones to

the corresponding bits in the ContextControl Set register.

Software can clear selected bits by writing ones to the cor-

responding bits in the ContextControl Clear register. It is

not possible for software to set some bits and clear others

in an atomic operation. A read from either register returns

the same.

4.4.25.4 Async Response Receive Command Pointer

The CommandPtr register specifies the address of the con-

text program which is executed when a DMA context is

started. All descriptors are 16-byte aligned, so the four

least-significant bits of any descriptor address must be

zero. The least-significant bit of the CommandPtr register is

used to encode a Z value. For each ARDMA context

(request and response) Z may be either 1 to indicate that

descriptorAddress points to a valid command descriptor, or

0 to indicate that there are no descriptors in the context

program.

Table 4-47. BAR0+Offset 1E0h (Set) and 1E4h (Clear): AsyncRespRxContextControl Register

Bit

Name

Access

Reset

Description

31:16

RSVD

Reserved

run

RSCU

Run: The run bit is set by software to enable descriptor processing for a

context and cleared by software to stop descriptor processing. The CS4210

only clears this bit on a hardware or software reset. See Section 3.3.2.1

"ContextControl.run" on page 21 for details.

14:13

RSVD

Reserved

wake

RSU

Undef

Wake: Software sets this bit to 1 to cause the CS4210 to continue or

resume descriptor processing. The CS4210 clears this bit on every descrip-

tor fetch. See Section 3.3.2.2 "ContextControl.wake" on page 21 for details.

dead

Dead: The CS4210 sets this bit when it encounters a fatal error. The

CS4210 clears this bit when software clears the run bit. See Section 3.3.2.4

"ContextControl.dead" on page 21 for details.

active

Active: The CS4210 sets this bit to 1 when it is processing descriptors. See

Section 3.3.2.3 "ContextControl.active" on page 21 for details.

9:8

RSVD

Reserved

7:5

spd

Undef

Speed: This field indicates the speed at which the last packet was received

by this context. 000 = 100 Mbits/sec, 001 = 200 Mbits/sec and 010 = 400

Mbits/sec. All other values are reserved. Software should not attempt to

interpret the contents of this field while the ContextControl.active or Contex-

tControl.wake bits are set.

4:0

eventcode

Undef

Event Code: The packet ack_ code or an “evt_” error code is indicated in

this field. Possible values are: ack_complete, ack_pending, ack_type_error,

evt_descriptor_read, evt_data_write, evt_bus_reset, evt_unknown, and

evt_no_status.

Table 4-48. BAR0+Offset 1ECh: AsyncRespRxCommandPtr Register

Bit

Name

Access

Reset

Description

31:4

descriptorAddress

RWU

Undef

Descriptor Address: Contains the upper 28 bits of the address of a 16-

byte aligned descriptor block. See Section 3.3.2.5 "CommandPtr" on page

22 for details.

3:0

RWU

Undef

ZBit: May be either 1 to indicate that descriptorAddress points to a valid

command descriptor, or 0 to indicate that there are no descriptors in the

context program.

CS4210 Datasheet(PDF) 83 Page - National Semiconductor (TI)

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