CS4210 datasheet(70/102 Pages) NSC

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4.4.16 Interrupts

The CS4210 reports two classes of interrupts to the host:

DMA interrupts and device interrupts. DMA interrupts are

generated when DMA transfers complete (or are aborted).

Device interrupts come directly from the remaining 1394

Open HCI logic. For example, one of these interrupts could

be sent in response to the asserting edge of cycleStart, a

signal which indicates that a new isochronous cycle has

started.

The CS4210 contains two primary 32-bit registers to report

and control interrupts: IntEvent and IntMask. Both registers

have two addresses: a “Set” address and a “Clear”

address. For a write to either register, a “one” bit written to

the “Set” address causes the corresponding bit in the regis-

ter to be set (excluding bits which are read-only), while a

“one” bit written to the “Clear” address causes the corre-

sponding bit to be cleared. For both addresses, writing a

“zero” bit has no effect on the corresponding bit in the reg-

ister.

The IntEvent register contains the actual interrupt request

bits. Each of these bits corresponds to either a DMA com-

pletion event, or a transition on a device interrupt line. The

IntMask register is ANDed with the IntEvent register to

enable selected bits to generate processor interrupts. Soft-

ware writes to the IntEvent Clear register to clear interrupt

conditions reported in the IntEvent register.

A processor interrupt is generated when one or more

unmasked bits are set in the IntEvent register. Low-level

software responds to the interrupt by reading the IntEvent

(assuming no new interrupt bit has been set). Software can

proceed to process the reported interrupts in whatever pri-

ority order it chooses, and is free to re-enable interrupts as

soon as the IntEvent Clear register is written.

In addition, the CS4210 contains four secondary 32-bit reg-

isters to report and control interrupts for isochronous trans-

mit and receive contexts. Each register has two addresses:

a “Set” address and a “Clear” address.

4.4.16.1 IntEvent Register

This register reflects the state of the various interrupt

sources from the 1394 Open HCI. The interrupt bits are set

by an asserting edge of the corresponding interrupt signal,

or by software by writing a one to the corresponding bit in

the IntEvent Set register. They are cleared by writing a one

to the corresponding bit in the IntEvent Clear register.

Reading the IntEvent Set register (BAR0+Offset 80h)

returns the current state of the IntEvent register. Reading

the IntEvent Clear register (BAR0+Offset 84h) returns the

masked version of the IntEvent register (IntEvent and Int-

Mask).

Table 4-26. BAR0+Offset 80h (Set) and 84h (Clear): IntEvent Register

Bit

Name

Access

Reset

Description

31:27

RSVD

Reserved

phyRegRcvd

RSCU

Undef

PHY Register Received: The CS4210 has received a PHY register data

byte which can be read from the PHY control register (see Section 4.4.20

"PHYControl Register" on page 77).

cycleTooLong

RSCU

Undef

Cycle Too Long: If LinkControl.cycleMaster (BAR0+Offset E0h[21] is set,

this indicates that an isochronous cycle lasted longer than the allotted time.

For implementations with a discrete cycleTooLong timer, hardware is

expected to trigger this event no less than 115 seconds and no more than

120 seconds after sending a cycle start packet unless a subaction gap or

bus reset indication is first observed. LinkControl.cycleMaster is cleared by

this event.

unrecoverableError

RSCU

Undef

Unrecoverable Error: This event occurs when the CS4210 encounters any

error that forces it to stop operations on any or all of its subunits. For exam-

ple, when a DMA context sets its contextControl.dead bit. While unrecover-

ableError is set, all normal interrupts for the context(s) that caused this

interrupt are blocked from being set.

cycleInconsistent

RSC

Undef

Cycle Inconsistent: A cycle start was received that had an isochronous

cycleTimer.seconds and isochronous cycleTimer.count different from the

value in the IsochCycleTimer register (BAR0+Offset F0h, see Section

4.4.21 "IsochCycleTimer Register" on page 77). The CS4210 indicates a

cycleInconsistent if a host initiated write changes the cycleSeconds or

cycleCount fields of the cycleTimer register. For the effect of this condition

on isochronous transmit and receive, refer to Section 3.8.3 "Isochronous

Transmit and Receive" on page 30.

cycleLost

RSCU

Undef

Cycle Lost: A lost cycle is indicated when no cycle_start packet is sent/

received between two successive cycleSynch events.

cycle64Seconds

RSCU

Undef

Cycle 64 Seconds: Indicates that the 7th bit of the cycle second counter

has changed.

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