CS4210 datasheet(73/102 Pages) NSC

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4.4.16.4 IsochTxIntEvent Register

There are two 32-bit registers to report isochronous trans-

mit context interrupts: IsochTxIntEvent and IsochTxInt-

Mask. Both registers are set and clear (Tables 4-28 and 4-

29). For all four addresses, writing a zero bit has no effect

on the corresponding bit in the register.

The IsochTxIntEvent register contains the actual interrupt

request bits. Each of these bits corresponds to a DMA

completion event for the indicated isochronous transmit

context. The IsochTxIntMask register is ANDed with the

IsochTxIntEvent register to enable selected bits to gener-

ate processor interrupts. If IsochTxIntMask and IsochTx-

IntEvent are not zero, then the IntEvent.IsochTxIntn bit is

set to one, and if enabled via the IntMask register it gener-

ates a processor interrupt. A software write to the IsochTx-

IntEvent Set register can therefore cause an interrupt (if not

otherwise masked). A software write to the IsochTx-

IntEvent Clear register clears interrupt conditions reported

in the IsochTxIntEvent register.

Reading the IsochTxIntEvent Set register returns the cur-

rent state of the IsochTxIntEvent register. Reading the

IsochTxIntEvent Clear register returns the masked version

of the IsochTxIntEvent register (IsochTxIntEvent and

IsochTxIntMask).

This IsochTxIntEvent register reflects the interrupt state of

the isochronous transmit contexts. An interrupt is gener-

ated on behalf of an isochronous transmit context if an

OUTPUT_LAST DMA command completes and its “i” field

is set to 11b (interrupt always). Upon determining that the

IntEvent.IsochTx interrupt has occurred, software can

check the IsochTxIntEvent register to determine which con-

text(s) caused the interrupt.

4.4.16.5 IsochTxIntMask Register

The bits in the IsochTxIntMask register (Table 4-29) have

the same format as the IsochTxIntEvent register. Setting a

bit in this register enables the corresponding bit in the

IsochTxIntEvent register. Setting a bit in this register is

done by setting the bit in the IsochTxIntMask Set register

(BAR0+Offset 98h) and cleared by writing a one to the cor-

responding bit in the IsochTxIntMask Clear register

(BAR0+Offset 9Ch). Bits for all unimplemented contexts

read as 0’s. Software can use this register to determine

which contexts are supported by writing to it with all 1’s,

then reading it back.Contexts witha1are implemented,

andthosewitha 0are not.

Table 4-28. BAR0+Offset 90h (Set) and 94h (Clear): IsochTxIntEvent Register

Bit

Name

Access

Reset

Description

31:8

RSVD

Reserved

isochTxInt7

RSCU

Undef

Isochronous Transmit Context Interrupt Event: Set to one when the cor-

responding isochronous transmit context interrupts and the interrupt mask

(BAR0+Offset 98h) is enabled.

6isochTxInt6

5isochTxInt5

4isochTxInt4

3isochTxInt3

2isochTxInt2

1isochTxInt1

0isochTxInt0

Table 4-29. BAR0+Offset 98h (Set) and 9Ch (Clear): IsochTxIntMask Register

Bit

Name

Access

Reset

Description

31:8

RSVD

Reserved

isochTxIntMask7

RSC

Undef

Isochronous Transmit Context Interrupt Mask: Set to one enables the

corresponding bit in the IsochTxintEvent register (BAR0+Offset 90h).

isochTxIntMask6

isochTxIntMask5

isochTxIntMask4

isochTxIntMask3

isochTxIntMask2

isochTxIntMask1

isochTxIntMask0

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