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PDP83TG720SWCSTQ1 Datasheet(PDF) 86 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 86 Page - Texas Instruments |
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86 / 199 page ![]() 7.6.2.30 TDR_STATUS2 Register (Address = 0x30B) [reset = 0x0] TDR_STATUS2 is shown in Table 7-53. Return to the Summary Table. Table 7-53. TDR_STATUS2 Register Field Descriptions Bit Field Type Reset Description 15-8 peak0_amp R 8b00000000 Peak 0 amplitude in echo coeff 7-0 peak4_loc R 8b00000000 Peak 4 location in tap index DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 86 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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