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PDP83TG720SWCSTQ1 Datasheet(PDF) 77 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 77 Page - Texas Instruments |
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77 / 199 page ![]() 7.6.2.21 LPS_STATUS Register (Address = 0x18E) [reset = 0x0] LPS_STATUS is shown in Table 7-44. Return to the Summary Table. Table 7-44. LPS_STATUS Register Field Descriptions Bit Field Type Reset Description 15-7 RESERVED R 9b00000000 0 Reserved 6-0 status_lps_st R 7b0000000 Observe LPS state : 0x2 = Standby mode 0x4 = Normal mode www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 77 |
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